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Benchmarking Quantum Data Center Architectures: A Performance and Scalability Perspective

Shahrooz Pouryousef, Eneet Kaur, Hassan Shapourian, Don Towsley, Ramana Kompella, Reza Nejabati

TL;DR

The paper tackles the problem of understanding how different quantum data-center architectures perform under realistic quantum hardware constraints. It introduces a unified benchmarking framework across four architectures—QFly, BCube, Clos, and Fat-Tree—and analyzes latency, resource contention, and scalability using a scatter--scatter entanglement model and architecture-specific routing/scheduling policies. Key contributions include quantitative comparisons under varying topologies, BSM provisioning models, and coherence constraints, revealing nontrivial interactions between topology, resource placement, and physical-layer losses. The findings highlight trade-offs: switch-centric fabrics excel in path diversity but suffer from switch-loss-driven bottlenecks, while server-centric BCube can benefit from shorter logical paths but faces memory- and coherence-related penalties as scale grows. The work provides actionable guidance for co-design of topology, scheduling, and photonic hardware to enable scalable, high-performance distributed quantum computation in data-center-like environments.

Abstract

Scalable distributed quantum computing (DQC) has motivated the design of multiple quantum data-center (QDC) architectures that overcome the limitations of single quantum processors through modular interconnection. While these architectures adopt fundamentally different design philosophies, their relative performance under realistic quantum hardware constraints remains poorly understood. In this paper, we present a systematic benchmarking study of four representative QDC architectures-QFly, BCube, Clos, and Fat-Tree-quantifying their impact on distributed quantum circuit execution latency, resource contention, and scalability. Focusing on quantum-specific effects absent from classical data-center evaluations, we analyze how optical-loss-induced Einstein-Podolsky-Rosen (EPR) pair generation delays, coherence-limited entanglement retry windows, and contention from teleportation-based non-local gates shape end-to-end execution performance. Across diverse circuit workloads, we evaluate how architectural properties such as path diversity and path length, and shared BSM (Bell State Measurement) resources interact with optical-switch insertion loss and reconfiguration delay. Our results show that distributed quantum performance is jointly shaped by topology, scheduling policies, and physical-layer parameters, and that these factors interact in nontrivial ways. Together, these insights provide quantitative guidance for the design of scalable and high-performance quantum data-center architectures for DQC.

Benchmarking Quantum Data Center Architectures: A Performance and Scalability Perspective

TL;DR

The paper tackles the problem of understanding how different quantum data-center architectures perform under realistic quantum hardware constraints. It introduces a unified benchmarking framework across four architectures—QFly, BCube, Clos, and Fat-Tree—and analyzes latency, resource contention, and scalability using a scatter--scatter entanglement model and architecture-specific routing/scheduling policies. Key contributions include quantitative comparisons under varying topologies, BSM provisioning models, and coherence constraints, revealing nontrivial interactions between topology, resource placement, and physical-layer losses. The findings highlight trade-offs: switch-centric fabrics excel in path diversity but suffer from switch-loss-driven bottlenecks, while server-centric BCube can benefit from shorter logical paths but faces memory- and coherence-related penalties as scale grows. The work provides actionable guidance for co-design of topology, scheduling, and photonic hardware to enable scalable, high-performance distributed quantum computation in data-center-like environments.

Abstract

Scalable distributed quantum computing (DQC) has motivated the design of multiple quantum data-center (QDC) architectures that overcome the limitations of single quantum processors through modular interconnection. While these architectures adopt fundamentally different design philosophies, their relative performance under realistic quantum hardware constraints remains poorly understood. In this paper, we present a systematic benchmarking study of four representative QDC architectures-QFly, BCube, Clos, and Fat-Tree-quantifying their impact on distributed quantum circuit execution latency, resource contention, and scalability. Focusing on quantum-specific effects absent from classical data-center evaluations, we analyze how optical-loss-induced Einstein-Podolsky-Rosen (EPR) pair generation delays, coherence-limited entanglement retry windows, and contention from teleportation-based non-local gates shape end-to-end execution performance. Across diverse circuit workloads, we evaluate how architectural properties such as path diversity and path length, and shared BSM (Bell State Measurement) resources interact with optical-switch insertion loss and reconfiguration delay. Our results show that distributed quantum performance is jointly shaped by topology, scheduling policies, and physical-layer parameters, and that these factors interact in nontrivial ways. Together, these insights provide quantitative guidance for the design of scalable and high-performance quantum data-center architectures for DQC.
Paper Structure (46 sections, 13 equations, 11 figures, 4 tables)

This paper contains 46 sections, 13 equations, 11 figures, 4 tables.

Figures (11)

  • Figure 1: Entanglement routing in server-centric architectures using QPUs as repeaters versus switch-centric optical switching architectures.
  • Figure 2:
  • Figure 3: A Fat-Tree architecture with pods. Each of the $k$ pods contains $k/2$ edge (top-of-rack) and $k/2$ aggregation switches that connect QPUs to a shared core layer of $(k/2)^2$ switches, providing full bisection bandwidth under uniform switch radix $k$.
  • Figure 4: Example QFly topology with $S=6$ switches, each serving $m=3$ QPUs ($N=18$). Each switch uses $k_{\mathrm{ring}}=2$ ports for inter-switch connectivity. By increasing $k_{\mathrm{ring}}$ we can reduce the number of hops between QPUs.
  • Figure 5: Example $(4,2)$-BCube topology with 16 QPUs. QPUs connect to two switch layers, with four switches per level. Communication paths may traverse intermediate QPUs, which act as repeaters in the server-centric BCube design.
  • ...and 6 more figures