Efficient implementation of single particle Hamiltonians in exponentially reduced qubit space

TL;DR

The paper tackles the challenge of computing spectra for solid-state Hamiltonians on near-term quantum devices with limited qubits. It introduces a logarithmic-qubit encoding that maps an $N$-site Hamiltonian to $n=\lceil \log_2 N\rceil$ qubits, paired with a SES-based variational circuit and a Gray-code measurement protocol, underpinned by a volumetric efficiency metric. The key contributions are (i) a binary-encoded SES ansatz preserving the original parameterization with exponential qubit reduction, (ii) a measurement scheme requiring only $2n+1$ global settings to recover all amplitudes and relative phases, and (iii) explicit scaling showing the space-time-sampling volume can drop from $O(N^2)$ to $O((\log N)^3)$ for hardware-efficient implementations. This approach enables large, structured solid-state Hamiltonians to be simulated on substantially smaller quantum registers on near-term devices, enhancing the practical reach of variational quantum algorithms for one-particle models.

Abstract

Current and near-term quantum hardware is constrained by limited qubit counts, circuit depth, and the high cost of repeated measurements. We address these challenges for solid state Hamiltonians by introducing a logarithmic-qubit encoding that maps a system with $N$ physical sites onto only $\lceil \log_2 N \rceil$ qubits while maintaining a clear correspondence with the underlying physical model. Within this reduced register, we construct a compatible variational circuit and a Gray-code-inspired measurement strategy whose number of global settings grows only logarithmically with system size. To quantify the overall hardware load, we introduce a volumetric efficiency metric that combines the number of qubit, circuit depth, and the number of measurement settings into a single measure, expressing the overall computation costs. Using this metric, we show that the total space-time-sampling volume required in a variational loop can be reduced dramatically from $N^2$ to $(logN)^3$ for hardware efficient ansatz, allowing an exponential reduction in time and size of the quantum hardware. These results demonstrate that large, structured solid-state Hamiltonians can be simulated on substantially smaller quantum registers with controlled sampling overhead and manageable circuit complexity, extending the reach of variational quantum algorithms on near-term devices.

Figures (6)

• Figure 1: Circuit representation of the SES ansatz. The localized excitation is propagated across the register through a sequence of two-qubit entangling gates $\hat{A}_{j,j+1}$ acting on neighboring qubits.
• Figure 2: Implementation of the $\hat{A}_{j,j+1}$ gate used in the SES ansatz. Each block is expressed in terms of three CNOTs and a sequence of parameterized single-qubit rotations $R_y$ and $R_z$.
• Figure 3: Two concatenated modules of the subspace-constrained ansatz. In each module, a two-qubit gate $A$ acts on the flag–selector pair $(a_0,a_1)$, followed by a SWAP. Conditioned on the flag, the data register is prepared in $|i\rangle$ (Module 1) and $|i{+}1\rangle$ (Module 2), and a multi-controlled toffoli operation targets $a_1$.
• Figure 4: Circular arrangement of the basis states $\ket{j},\ket{j+1},\ldots,\ket{j+7}$ used to extract phase differences. The blue edge shows the local relative phase $\delta\theta_j=\theta_{j+1}-\theta_j$, while the red arc illustrates the cumulative phase difference across multiple steps, $\theta_{j+4}-\theta_{j+2}=\sum_{r=2}^{3}(\theta_{j+r+1}-\theta_{j+r})$.
• Figure 5: The protocol consists of quantum measurements to extract amplitudes and relative phases, followed by classical post-processing to reconstruct the total energy.