Phase transitions in time complexity of Brownian circuits

TL;DR

This work analyzes time complexity in Brownian circuits by recasting computation as a stochastic first-passage problem on state-transition diagrams. It identifies an easy-hard transition in mean first-passage time as the forward rate $\gamma_+$ crosses a critical value $\gamma_c$, with linear, quadratic, or exponential scaling depending on effective drift; a universal $\alpha=2$ scaling emerges at the transition in one-dimensional limits. The SoP (sum-of-products) circuit realizes a near-one-dimensional structure with $a=1$, predicting $\gamma_c=\gamma_-$ but at exponential space cost, while modular adders exhibit $\gamma_c>\gamma_-$ due to merging paths, illustrating a fundamental time-space-energy trade-off. Overall, the paper provides a complexity-theoretic lens on fluctuation-driven computation, showing that a finite energy input is typically required for polynomial-time computation in Brownian circuits and guiding design principles toward serial, near-one-dimensional architectures.

Abstract

Brownian circuits implement computation through stochastic transitions driven by thermal fluctuations. While the energetic costs of such fluctuation-driven computation have been extensively studied within stochastic thermodynamics, much less is known about its computational complexity, in particular how computation time scales with circuit size. Here, the computation time of explicitly designed Brownian circuits is investigated numerically via the first-passage time to a completed state. For arithmetic circuits such as adders, varying the forward transition rate induces a sharp change in the scaling behavior of the mean computation time, from linear to exponential in circuit size. This change can be interpreted as an easy-hard transition in computational time complexity. The transition suggests that, for meaningful computational tasks, achieving efficient polynomial-time computation generically requires a finite forward bias, corresponding to a nonzero energy input. As a counterexample, it is shown that arbitrary logical operations can be reduced to an effectively one-dimensional stochastic process, for which the zero-bias limit lines within the computationally efficient (easy) regime. However, realizing such a one-dimensional normal form unavoidably leads to an exponential increase in circuit size. These results reveal a fundamental trade-off between computation time, circuit size, and energy input in Brownian circuits, and demonstrate that phase transitions in time complexity provide a natural framework for characterizing the cost of fluctuation-driven computation.

Figures (16)

• Figure 1: A schematic diagram of the CJoin gate and its two possible states. The gate is represented by a box with four wires: top, bottom, left, and right. These wires are grouped into two pairs: top-left and bottom-right, as indicated by the arrows inside the box. The two filled circles represent particles. In state (a), the particles occupy the top and left wires, while in state (b), they occupy the right and bottom wires. The gate transitions between these two states.
• Figure 2: NAND circuit and its transition process in a Brownian circuit: $A$ and not $B$ are the inputs. The circuit progresses through four states to reach the True output. White boxes represent CJoin gates, black circles represent connected junctions of wires, and blue circles represent Brownian particles. (a) Initial state: Brownian particles are placed on wires $A$ and "not $B$". (b) Particles search for the correct gate by moving along their respective wires. (c) A gate transition moves the particles to the next wires. (d) Final state: The particles reach the output wires, resulting in the True output.
• Figure 3: (a) A two-particle I/O circuit explicitly constructed using CJoin gates. (b) Boxing representation of the same circuit. The number $4$ inside the box indicates the number of gates used in this module. Each input logical variable is represented by a pair of wires, with the number $2$ indicating the number of input wires. The eight output wires (four on the right and four on the bottom in panel (a)) are grouped into two pairs and represented compactly. The interpretation of each output is context-dependent and specified as needed.
• Figure 4: Boxing representation of a NAND circuit. The output $\overline{A\cdot B}$ is represented by two wires, also labeled as $2$. The label $4$ at the bottom-right indicates four unused wires.
• Figure 5: Full adder circuit. A conventional full adder adapted to a Brownian circuit. $A$ and $B$ are the bits to be added, $C$ is the "carry-in" from the lower digit, $X= A \oplus B \oplus C$ is the output of addition, and $G = {A} \cdot {B} + ({A} \oplus {B}) \cdot C$ is the "carry-out" to the upper digit.