Volcano Architecture for Scalable Quantum Processor Units

TL;DR

The Volcano architecture tackles the scaling challenge of addressing and reading out large qubit arrays by introducing optical channel mapping (OCM) that translates a 2D qubit layout into a 1D optical-channel network, thereby unifying the classical control and quantum readout interconnects. A 3D photonic chip fabricated by femtosecond-laser writing demonstrates the concept, enabling a $49$-channel OCM with low crosstalk and high uniformity, and offering ultralow loss and broad wavelength operation. The approach supports modular, chip-to-chip interconnects and is compatible with neutral atoms, trapped ions, and quantum dots, paving the way for scalable QPUs and quantum networking. The work shows that integrating C-links and Q-links through OCM can realize scalable, programmable optical interconnects, potentially forming the backbone of distributed quantum computing architectures and heterogeneous quantum networks.

Abstract

Quantum information processing platforms based on array of matter qubits, such as neutral atoms, trapped ions, and quantum dots, face significant challenges in scalable addressing and readout as system sizes increase. Here, we propose the "Volcano" architecture that establishes a new quantum processing unit implementation method based on optical channel mapping on a arbitrarily arranged static qubit array. To support the feasibility of Volcano architecture, we show a proof-of-principle demonstration by employing a photonic chip that leverages custom-designed three-dimensional waveguide structures to transform one-dimensional beam arrays into arbitrary two-dimensional output patterns matching qubit array geometries. We demonstrate parallel and independent control of 49-channel with negligible crosstalk and high uniformity. This architecture addresses the challenges in scaling up quantum processors, including both the classical link for parallel qubit control and the quantum link for efficient photon collection, and holds the potential for interfacing with neutral atom arrays and trapped ion crystals, as well as networking of heterogeneous quantum systems.

Figures (6)

• Figure 1: The element and scale-up of quantum processor units. (a) Schematic representation of the basic setup for single qubit control and readout. Electric signals and continuous wave lasers are used to control the external and internal degrees of freedom of the qubits, and the qubits entangle with single photons through emission, and their quantum states can be detected or entangled with other qubits by collecting and directing the photons into optical fibers. (b) Illustration of the scaling challenges in quantum processors, highlighting the need for efficient addressing control and photon collection for individual qubits in an two-dimensional array. The classical link (depicted on the left) provides the necessary optical signals to control and manipulate individual qubits in the quantum processor. The quantum link (depicted on the right) enables the coupling of qubits to photons for measurement and the distribution of entanglement among QPUs. The readout process involves detecting photon emissions from qubits through a fiber array and single-photon detectors.
• Figure 2: Volcano architecture. Left panel: overview of the Volcano architecture, showing how a 2D qubit array is mapped onto a 1D optical channel network via an optical channel mapping (OCM) component. Upper-right panel: candidate platforms for realizing the qubit array, including: neutral atoms in optical tweezer arrays; 2D ion crystals; spin qubits implanted in substrates. Lower-right panel: available optical elements with massive independent channels for distributing, manipulating, and detecting photons, including: For C-links: reconfigurable 1D laser beam arrays generated by AODs, vertical cavity surface emitting lasers (VCSEL) arrays; For Q-links: standard commercial fiber array, single-photon detector (SPD) arrays; For both: planar waveguide arrays on high-refractive index contrast photonic chips.
• Figure 3: 3D photonic chip for Volcano architecture implementation. (a) A 3D photonic chip fabricated using laser direct writing technology and placed on motorized stages (on the left), with coupling between the photonic chip and a fiber array (on the right). (b) Topology design of 49 waveguides in the photonic chip. (c-d) Schematics of the input and output facets of the 3D photonic chip. (e) One implementation method of the Volcano architecture is based on the 3D photonic chip. Different colors represent distinct channels for different qubits. The left shows classic optical channels, while the right shows quantum optical channels.
• Figure 4: Calculation of waveguides in photonic chip. (a) Mode field distribution of the fundamental waveguide mode. The black circle indicates stepwise refractive index boundaries. (b) Square points (left axis) are the wavelength-dependent mode field diameter (MFD) in the waveguide, while circular points (right axis) show the coupling efficiency between the waveguide and a Gaussian beam with the corresponding MFD. (c) Data points show the couple constant versus waveguide distance between two parallel waveguides at three specific wavelengths. Solid curves illustrate fitting results consistent with coupled-mode theory predictions. (d) Crosstalk characterization between two waveguides at a fixed effective coupling length of 5 mm. Colored markers quantify crosstalk across varying wavelengths with several coupling distances.
• Figure 5: Characterization of waveguides in photonic chip. (a) Imaging results after 49 channels are fully activated, recorded by a CCD after guidance through the 3D photonic chip. (b) Characterization of uniformity of 49 channels: the relative standard deviation (RSD) is $95.5\%$. (c) Imaging result of the addressing demonstration “ US”. (d) Imaging result of the addressing demonstration “TC”. (e) Crosstalk matrix for the 49 channels, where rows indicate enabled channel IDs and columns represent the corresponding imaged channel IDs. Matrix entries quantify optical intensity measured in target columns when each row channels are individually enabled. The maximum, average nearest-input, and average nearest-output crosstalk values are measured as $1.198\%$ , $0.232\%$, and $0.158\%$, respectively.