Syndrome aware mitigation of logical errors

TL;DR

This work introduces syndrome-aware logical error mitigation (SALEM), a practical framework to maximize the benefit of error correction when mitigating logical errors using error mitigation (EM). By leveraging syndrome data collected during error correction, SALEM partitions the syndrome space into either fine-grained or coarse-grained subsets and applies syndrome-conditioned EM protocols, weighted by inverse-variance to minimize shot overhead. The approach yields unbiased estimators with substantially reduced QPU-time overhead, outperforming ExtLEM and EC+PS, and can surpass the standard fault-tolerance threshold in effective circuit volume. Demonstrations on Steane and surface-code benchmarks, along with analytical results on blowup rates and thresholds, indicate SALEM’s potential to substantially extend the operable regime of near-term quantum devices while closely integrating EC with EM.

Abstract

Broad applications of quantum computers will require error correction (EC). However, quantum hardware roadmaps indicate that physical qubit numbers will remain limited in the foreseeable future, leading to residual logical errors that limit the size and accuracy of achievable computations. Recent work suggested logical error mitigation (LEM), which applies known error mitigation (EM) methods to logical errors, eliminating their effect at the cost of a runtime overhead. Improving the efficiency of LEM is crucial for increasing the logical circuit volumes it enables to execute. We introduce syndrome-aware logical error mitigation (SALEM), which makes use of the syndrome data measured during error correction, when mitigating the logical errors. The runtime overhead of SALEM is exponentially lower than that of previously proposed LEM schemes, resulting in significantly increased circuit volumes that can be executed accurately. Notably, relative to the routinely used combination of error correction and syndrome rejection (post-selection), SALEM increases the size of reliably executable computations by orders of magnitude. In this practical setting in which space and time are both resources that need to be optimized, our work reveals a surprising phenomenon: SALEM, which tightly combines EC with EM, can outperform physical EM even above the standard fault-tolerance threshold. Thus, SALEM can make use of EC in regimes of physical error rates at which EC is commonly deemed useless.

Figures (15)

• Figure 1: Conceptual overview of syndrome-aware logical error mitigation (SALEM). (a) An error-corrected logical circuit, ending with the measurement of a logical observable $O$. Within each logical gate, physical errors occur (pink zigzags), and a syndrome bit-string $s$ is measured, decoded ($D$), and used to recover ($R_s$) from the most probable physical error processes given the syndrome. Red zigzags indicate logical errors due to less probable physical error processes. (b) The logical error channel $\Lambda_L$ corresponds to the (syndrome-averaged) distribution of logical errors at the output of a logical gate, see Sec. \ref{['Sec: setup']}. (c) Direct estimation of the expectation value $\langle O\rangle$ is biased, due to the non-trivial logical error channel, $\Lambda_L\neq I$. (d) Previously proposed 'external logical error mitigation' (ExtLEM) applies a fixed error mitigation (EM) protocol $EM$, irrespective of the measured syndrome $s$. The protocol is designed to mitigate the channel $\Lambda_L$, producing an unbiased estimator $o$ for $\langle O \rangle$, at the expense of an increased statistical error (for a fixed number of shots). (e) Restricting attention to shots in which a particular value of the syndrome $s$ was measured, the $s$-conditioned logical error channel $\Lambda_{L|s}$ appears as the relevant error channel. (f) 'Syndrome-aware logical error mitigation' (SALEM), introduced here, applies a separate EM protocol $EM_s$, designed to mitigate the channel $\Lambda_{L|s}$, to shots in which the syndrome $s$ is measured. The resulting unbiased estimators $o_{s}$ for different syndromes are averaged with 'inverse-variance' weights $w_s$, producing an unbiased estimator $\overline{o}$ with a significantly reduced shot overhead. (g) A standard approach to mitigating logical errors using syndrome data is 'post-selection' (EC+PS), which can be described as a simple averaging with binary weights, corresponding to 'accepted' or 'rejected' syndromes, without applying mitigation in the accepted case. This leads to a remaining bias due to logical errors in accepted syndromes (as well as a sub-optimal increase in variance due to rejected syndromes).
• Figure 2: Performance benefits of (coarse-grained) SALEM. (a) Comparison of estimators for an expectation value $\langle Z\rangle$ due to different error reduction methods, as a function of logical circuit volume $V$, normalized with the logical error rate $\epsilon_L\approx10^{-4}$, for a fixed physical error $\epsilon=10^{-3}$. EC is based on a distance 4 surface code memory circuit subject to circuit-level physical errors, see Fig. \ref{['Fig: Bi-SALEM']} and Appendix \ref{['Appendix: numerical simulations']} for technical details. All error reduction methods are allocated the same space and time overheads, relative to the number of qubits and the runtime needed to meet the allowed estimation error ($1\%$, gray dashed lines) in an idealized error-free QPU. Specifically, we allocate a space-time volume corresponding to one-hundred error-corrected shots per error-free shot. The physical methods Bare and EM exploit the given space overhead by parallelizing shots, and have a lower shot time than methods involving EC. Shaded bands show the expected statistical spread of estimators (mean $\pm$ one standard deviation), with mean curves shown only for biased methods and points illustrating a representative finite-shot realization. SALEM outperforms all methods, maintaining the required accuracy for significantly larger circuit volumes. (b) The 'circuit volume boost' (CVB) is the multiplicative improvement in achievable volume for a given required accuracy WhyEM. Methods limited by bias (EC and EC+PS), can provide significant CVBs, which do not change much with allowed inaccuracy $\delta$. Methods limited by statistical errors (EM, ExtLEM and SALEM), provide a CVB $\sim \delta^{-1}$, and are therefore superior at small $\delta$ (high required accuracy). SALEM achieves the largest circuit volumes among all methods, at both high and low accuracy. (c) The behavior of estimation errors (including both biases and statistical errors) for the different methods as a function of physical error rate reveals the standard 'FT (pseudo) threshold' (gray dot), as well as two new types of (pseudo) thresholds, obtained by comparing ExtLEM and SALEM to physical EM (black dots). The logical circuit volume is scaled relative to the physical error rate, $V=2.5/\epsilon$, such that the Bare and EM methods have constant estimation errors. At practical volumes $V=O(1/\epsilon_L)$, the SALEM threshold is larger than the FT threshold.
• Figure 3: Performance of coarse-grained (binary) SALEM. Top panels: Blowup rates $\lambda^{\{S_0,S_1\}}_{SALEM}$ for different variants of CG-SALEM based on binary partitions $S=S_0\cup S_1$ of syndromes ('binary CG-SALEM'). The 'good' set $S_0$ should have a small conditioned logical error $\epsilon_{L|0}$, and is mitigated using local inversion ($\text{Inv}_0$). The 'bad' set $S_1$ should have a large conditioned logical error $\epsilon_{L|1}$, and is mitigated by rejection (blue), local inversion (orange) or mid-shot rejection (cyan). In each panel, the bad set $S_1$ shrinks from $S$ to $\emptyset$ along the x-axis. Minimal values of $\lambda_{LEM}$ for each binary CG-SALEM variant indicate the optimal partition for that variant. The $(\text{Inv}_0,\text{Inv}_1)$ variant always improves upon both ExtLEM (based on local inversion) and $(\text{Inv}_0,\text{Rej}_1)$, but requires that classification be performed in real-time and does not significantly improve upon $(\text{Inv}_0,\text{Rej}_1)$ when using (near-) optimal partitions. Mid-shot rejection also requires a real-time classifier, and $(\text{Inv}_0,\text{MS\_Rej}_1)$ can provide the best blowup rate (of QPU time) among the three variants, depending on the depth of the mitigated logical circuit (data shown corresponds to depth $D=\epsilon_L^{-1}$). The data is obtained from simulations of logical memory circuits for the $d=4$ surface code, decoded using the MWPM algorithm pymatching, representing a sub-optimal 'realistic' decoder. We consider two families of classifiers: one based on the MWPM decoder itself (Left Panels) smith2024mitigatingmeister2024efficientsoftoutputdecoderssurfacegidney2023yokedsurfacecodes, which can therefore run in real-time; and a stronger but slower family of classifiers based on a TN decoder (Right Panels) piveteau2023tensornetworkdecoding, which may only be possible to run in post-process. The x-axes correspond to a threshold that defines a specific classifier within each family, setting a cutoff on a decoder-derived proxy for the conditional logical error (see Appendix \ref{['Appendix: numerical simulations']}). Numerically obtained blowup rates are well approximated by simple expressions in terms of $\epsilon_{L|1}=\mathbb{P}(\text{logical error}|S_1)$ and $p_{1|L}=\mathbb{P}(S_1|\text{logical error})$, the latter representing the fraction of logical errors 'contained' in the set $S_1$ (see top legend and Appendix \ref{['Appendix: bi-SALEM']}-\ref{['Appendix: mid-shot reject']}). These quantities are plotted in the Bottom Panels. Maximizing both $\epsilon_{L|1}$ and $p_{1|L}$ is desirable but impossible, and optimal partitions are obtained when the two are balanced.
• Figure 4: The iterative construction of logical error channels from physical error channels. The scheme shows how by using Eq. (\ref{['Eq: L->next in']}) iteratively, the physical channels are replaced by logical channels and a fully logical description is reached in Eq. (\ref{['eq:G_to_g']}) . Reddish blocks denote physical operations acting on the full physical Hilbert space, while white (unshaded) blocks denote logical operations restricted to code subspace.
• Figure 5: Intuition for Lemma \ref{['lemma1']} and Proposition \ref{['thm0']} with $t=2$. Each panel shows three consecutive gates, with faults marked by $\times$'s. (a) The $2$-FT property implies at most one output error after $G_{j-1}$, so the additional fault in $G_j$ is not enough to cause a logical error. (b) $G_j$ has at most one input error and two faults, so a logical error after $G_j$ can occur. However this is a sub-leading weight-4 fault-path. (c) A leading order logical error may occur after $G_{j-1}$, but is included in the approximate logical channel of $G_{j-1}$, not of $G_j$. (d) A potential leading order logical error after $G_j$.

Theorems & Definitions (8)

• Lemma 1
• Proposition 1
• Theorem 1
• Theorem 2
• Theorem 3
• Example 1
• Corollary 1
• Example 2