Enabling Physical AI at the Edge: Hardware-Accelerated Recovery of System Dynamics

TL;DR

This work tackles enabling real-time, explainable model recovery for physical AI deployed at the edge under strict resource limits. It replaces iterative Neural ODE solvers with a GRU-based neural-flow formulation implemented on FPGA, augmented by dense inverse-ODE layers, sparsity-driven dropout, and lightweight solvers, achieving hardware-friendly parallelism. The approach, MERINDA, matches state-of-the-art MR accuracy while delivering dramatic gains in energy efficiency, memory footprint, and training speed, and is guided by a MILP framework to select optimal platform-task configurations. The findings demonstrate that hardware-algorithm co-design can unlock practical, on-device MR for safety-critical autonomous systems, with broad implications for edge AI and potential extension to other domains like LLMs.

Abstract

Physical AI at the edge -- enabling autonomous systems to understand and predict real-world dynamics in real time -- requires hardware-efficient learning and inference. Model recovery (MR), which identifies governing equations from sensor data, is a key primitive for safe and explainable monitoring in mission-critical autonomous systems operating under strict latency, compute, and power constraints. However, state-of-the-art MR methods (e.g., EMILY and PINN+SR) rely on Neural ODE formulations that require iterative solvers and are difficult to accelerate efficiently on edge hardware. We present \textbf{MERINDA} (Model Recovery in Reconfigurable Dynamic Architecture), an FPGA-accelerated MR framework designed to make physical AI practical on resource-constrained devices. MERINDA replaces expensive Neural ODE components with a hardware-friendly formulation that combines (i) GRU-based discretized dynamics, (ii) dense inverse-ODE layers, (iii) sparsity-driven dropout, and (iv) lightweight ODE solvers. The resulting computation is structured for streaming parallelism, enabling critical kernels to be fully parallelized on the FPGA. Across four benchmark nonlinear dynamical systems, MERINDA delivers substantial gains over GPU implementations: \textbf{114$\times$ lower energy} (434~J vs.\ 49{,}375~J), \textbf{28$\times$ smaller memory footprint} (214~MB vs.\ 6{,}118~MB), and \textbf{1.68$\times$ faster training}, while matching state-of-the-art model-recovery accuracy. These results demonstrate that MERINDA can bring accurate, explainable MR to the edge for real-time monitoring of autonomous systems.

Figures (4)

• Figure 1: Optimization Framework of MERINDA. At the high level, we reformulate MR by replacing the iterative ODE solver in Liquid Time-Constant networks(LTC) with a GRU-based neural flow. At the low level, we specialize the GRU-based MR for FPGA by fine-grained spatial parallelism.
• Figure 2: FPGA acceleration strategy using neural flow based equivalent architecture to neural ODEs.
• Figure 3: MERINDA: Gated recurrent unit (GRU) NN-based MR architecture.
• Figure 4: Mixed Integer Linear Program to obtain optimal approach and hyperparameters for MR, ML or ML-PG.