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An Electronic Ising Machine

Matt Bowring, Ben Anderson, Ben Tiffany

TL;DR

This work presents an electronic Ising machine built from a mixed-signal PCB that uses a network of LC oscillators to solve NP-hard graph problems via energy minimization. It encodes the Ising couplings in a fully connected oscillator network through programmable resistive paths and uses an external SYNC to enforce binary phase states, enabling annealing-like optimization. Kuramoto-type phase dynamics with a Lyapunov energy guide the system toward low-energy configurations, and simulations plus breadboard experiments validate the approach on Max-Cut tasks. The study highlights practical scaling challenges and points to future research directions, including optimal-control formulations for SYNC and energy-efficient scaling to larger oscillator counts.

Abstract

We develop a custom printed circuit board (PCB) for a low-power and high-speed accelerator of NP-Hard graph problems. The architecture implements an annealing-based computing paradigm using a network of nonlinear electronic oscillators whose phase dynamics converge to stable configurations that encode solutions. We review the theoretical framework, and present our circuit design, simulations, and experimental results. We further highlight some key future research directions for the emerging developing of computing architectures based on energy minimization.

An Electronic Ising Machine

TL;DR

This work presents an electronic Ising machine built from a mixed-signal PCB that uses a network of LC oscillators to solve NP-hard graph problems via energy minimization. It encodes the Ising couplings in a fully connected oscillator network through programmable resistive paths and uses an external SYNC to enforce binary phase states, enabling annealing-like optimization. Kuramoto-type phase dynamics with a Lyapunov energy guide the system toward low-energy configurations, and simulations plus breadboard experiments validate the approach on Max-Cut tasks. The study highlights practical scaling challenges and points to future research directions, including optimal-control formulations for SYNC and energy-efficient scaling to larger oscillator counts.

Abstract

We develop a custom printed circuit board (PCB) for a low-power and high-speed accelerator of NP-Hard graph problems. The architecture implements an annealing-based computing paradigm using a network of nonlinear electronic oscillators whose phase dynamics converge to stable configurations that encode solutions. We review the theoretical framework, and present our circuit design, simulations, and experimental results. We further highlight some key future research directions for the emerging developing of computing architectures based on energy minimization.
Paper Structure (12 sections, 7 equations, 11 figures, 1 table)

This paper contains 12 sections, 7 equations, 11 figures, 1 table.

Table of Contents

  1. Introduction
  2. Methodology
  3. Theory
  4. Oscillator Board
  5. Coupling Board
  6. Synchronization
  7. Programming
  8. Evaluation
  9. Simulation
  10. Experiments
  11. Discussion
  12. Contributions

Figures (11)

  • Figure 1: The complete assembly of our circuit. It encodes the problem matrix using a network of inductor-capacitor (LC) oscillators that are fully-connected with programmable resistors.
  • Figure 2: The oscillator board. The switch is used to toggle power to the oscillators.
  • Figure 3: The coupling board with a mounted ESP32 microcontroller.
  • Figure 4: Block diagram connections between the microcontroller, the decoder, and the digital potentiometers.
  • Figure 5: The two R/2R resistor ladder designs considered for implementing a single tunable resistor (e.g., $R_{12}$). Neither of the designs were used in the circuit.
  • ...and 6 more figures