The Dawn of Agentic EDA: A Survey of Autonomous Digital Chip Design

TL;DR

The paper analyzes the shift from AI-assisted EDA to AI-native, agentic EDA, arguing that autonomous reasoning, planning, and tool orchestration across RTL to GDSII are needed to tackle the Productivity Gap. It synthesizes foundational components (CFMs and domain-adapted LLMs), front-end and back-end agentic workflows, cross-stage feedback, and security/infrastructure concerns, supported by integrated case studies and benchmarks. Key contributions include a formal autonomy framework, architectural patterns for agentic cognition, and evidence of cross-stage optimization driving PPA improvements, alongside a candid discussion of challenges such as hallucinations and data scarcity. The work provides a strategic roadmap toward AI-Native autonomous chip design with an emphasis on end-to-end evaluation, open datasets, and hybrid neuro-symbolic approaches to ensure correctness and trust at scale.

Abstract

This survey provides a comprehensive overview of the integration of Generative AI and Agentic AI within the field of Digital Electronic Design Automation (EDA). The paper first reviews the paradigmatic evolution from traditional Computer-Aided Design (CAD) to AI-assisted EDA (AI4EDA), and finally to the emerging AI-Native and Agentic design paradigms. We detail the application of these paradigms across the digital chip design flow, including the construction of agentic cognitive architectures based on multimodal foundation models, frontend RTL code generation and intelligent verification, and backend physical design featuring algorithmic innovations and tool orchestration. We validate these methodologies through integrated case studies, demonstrating practical viability from microarchitecture definition to GDSII. Special emphasis is placed on the potential for cross-stage feedback loops where agents utilize backend PPA metrics to autonomously refine frontend logic. Furthermore, this survey delves into the dual-faceted impact on security, covering novel adversarial risks, automated vulnerability repair, and privacy-preserving infrastructure. Finally, the paper critically summarizes current challenges related to hallucinations, data scarcity, and black-box tools, and outlines future trends towards L4 autonomous chip design. Ultimately, this work aims to define the emerging field of Agentic EDA and provide a strategic roadmap for the transition from AI-assisted tools to fully autonomous design engineers.

Figures (6)

• Figure 1: Evolution of IC Design Paradigms toward Autonomy. The figure depicts a four-stage trajectory: evolving from passive (1) Manual/CAD tools and (2) fragmented AI4EDA patches, to a unified (3) AI-Native EDA foundation, and finally realizing (4) Intelligent Design 4.0 driven by autonomous agents with reasoning-acting-reflecting loops.
• Figure 2: The cognitive architecture of an EDA Agent. It integrates Multimodal Perception (via CFMs), Retrieval-Augmented Memory (RAG), and a ReAct-based Tool Execution loop to interact with standard EDA toolchains.
• Figure 3: The Dual-Loop Architecture of Agentic RTL Repair. The Inner Loop (e.g., AutoChip autochip) relies on textual compiler logs to fix syntax. The Outer Loop (e.g., VerilogCoder ho_verilogcoder_2025) bridges the modality gap by tracing simulation waveforms via AST analysis, converting signal mismatches into natural language feedback for semantic logic repair.
• Figure 4: Visual comparison of physical design paradigms: (a) Reinforcement Learning treats placement as a sequential game; (b) Diffusion Models generate layouts via parallel denoising; (c) Agentic approaches optimize PPA by tuning toolchain parameters rather than direct geometric manipulation.
• Figure 5: Paradigm Shift in Macro Placement: From Sequential to Generative. (a) Reinforcement Learning (e.g., AlphaChip) treats placement as a sequential game, where inference time grows linearly with macro count. (b) Diffusion Models (e.g., DCTdiff ning_dctdiff_2025) formulate placement as a parallel denoising process, learning the joint probability distribution of valid layouts to enable zero-shot generalization.