SOFT: a high-performance simulator for universal fault-tolerant quantum circuits

TL;DR

SOFT addresses the challenge of reliably simulating universal fault-tolerant quantum circuits with non-Clifford gates by integrating a generalized stabilizer formalism with GPU-accelerated, shot-parallel computation. The framework enables ground-truth, high-scale simulations of noisy Clifford+$T$ circuits, demonstrated through the distance-$5 magic state cultivation protocol that contains 42 qubits and 72 non-Clifford gates. Key findings reveal a significant discrepancy between actual logical error rates and prior Clifford-proxy predictions, underscoring the necessity of accurate non-Clifford verification for architectural design. The work delivers a scalable, open-source tool that shifts the emphasis from quantum memory to universal quantum computation, with broad implications for resource estimation and optimizer development in fault-tolerant quantum computing.

Abstract

Circuit simulation tools are critical for developing and assessing quantum-error-correcting and fault-tolerant strategies. In this work, we present SOFT, a high-performance SimulatOr for universal Fault-Tolerant quantum circuits. Integrating the generalized stabilizer formalism and highly optimized GPU parallelization, SOFT enables the simulation of noisy quantum circuits containing non-Clifford gates at a scale not accessible with existing tools. To provide a concrete demonstration, we simulate the state-of-the-art magic state cultivation (MSC) protocol at code distance $d=5$, involving 42 qubits, 72 $T$ / $T^\dagger$ gates, and mid-circuit measurements. Using only modest GPU resources, SOFT performs over 200 billion shots and achieves the first ground-truth simulation of the cultivation protocol at a non-trivial scale. This endeavor not only certifies the MSC's effectiveness for generating high-fidelity logical $T$-states, but also reveals a large discrepancy between the actual logical error rate and the previously reported values. Our work demonstrates the importance of reliable simulation tools for fault-tolerant architecture design, advancing the field from simulating quantum memory to simulating a universal quantum computer.

Figures (4)

• Figure 1: $d=3$ MSC circuit excluding the noise channels and the final Pauli product measurements.
• Figure 2: Logical error rate of $d=5$ magic state injection + cultivation at several physical error rates. Color highlights represent statistical uncertainty arising from Monte Carlo sampling. Each highlight spans hypothetical logical error rates that have a Bayes factor of no more than 1000 relative to the maximum likelihood hypothesis, under the assumption of a binomial distribution
• Figure 3: The sampling throughput versus batch_size on a single H800 GPU, with $d$=5 MSC circuit and $p=0.001$. Here, orange dashed line means the theoretical maximum number of resident threads of H800 PCIe: 114 $\mathrm{SMs}\ \times$ 2048 threads/SM = 233,472 threads.
• Figure 4: The sampling throughput versus noise strength $p$ on a single H800 GPU, with code distance $d$=5. During these experiments, we always set the batch_size to be $2^{18} = 262,144$.

Theorems & Definitions (6)

• Definition 1: Generalized stabilizer representation yoder2012generalization
• Theorem 1: Update cost and sparsity bound yoder2012generalization
• proof
• Proposition 1: Coset bound for a $T$-layer
• proof : Proof sketch
• Theorem 2: Upper bound of $|\mathbf{v}|$