AnalogSAGE: Self-evolving Analog Design Multi-Agents with Stratified Memory and Grounded Experience

TL;DR

AnalogSAGE addresses the reliability gap in automated analog design by coupling three stage agents (Topology Selection, Topology Refinement, Parameter Optimization) with four stratified memory layers that integrate simulation feedback. The framework employs retrieval-augmented knowledge, a topology vector database, and Bayesian optimization to ground reasoning in practical PDK conditions, achieving substantial improvements in pass rates, convergence speed, and search-space efficiency on ten specification-driven op-amp tasks. Across experiments, the combination of Evolution Memory and Introspective Optimization yields robust performance, with a 100% pass rate and a 4x reduction in parameter search space, demonstrating meaningful gains in autonomy and reliability for analog design automation. The open-source release further enables reproducibility and fair benchmarking in this domain.

Abstract

Analog circuit design remains a knowledge- and experience-intensive process that relies heavily on human intuition for topology generation and device parameter tuning. Existing LLM-based approaches typically depend on prompt-driven netlist generation or predefined topology templates, limiting their ability to satisfy complex specification requirements. We propose AnalogSAGE, an open-source self-evolving multi-agent framework that coordinates three-stage agent explorations through four stratified memory layers, enabling iterative refinement with simulation-grounded feedback. To support reproducibility and generality, we release the source code. Our benchmark spans ten specification-driven operational amplifier design problems of varying difficulty, enabling quantitative and cross-task comparison under identical conditions. Evaluated under the open-source SKY130 PDK with ngspice, AnalogSAGE achieves a 10$\times$ overall pass rate, a 48$\times$ Pass@1, and a 4$\times$ reduction in parameter search space compared with existing frameworks, demonstrating that stratified memory and grounded reasoning substantially enhance the reliability and autonomy of analog design automation in practice.

Figures (4)

• Figure 1: Overview of the proposed framework with three main stages: topology selection, topology refinement, and parameter optimization. The dashed line indicates closed-loop feedback. Each stage agent is supported by four memory layers that provide essential context for the LLM to perform iterative design improvements.
• Figure 2: Interaction between the four context layers and the stage agents: Evolution Memory, Introspective Optimization, Stage Context Fusion, and Analog Design Experience. Each design iteration updates different parts of the memory layers based on the generated results.
• Figure 3: Construction workflow of the Topology Vector Database. Each topology is converted into a two-sentence textual representation and stored as a key--value pair, where the embedded description serves as the key and the netlist as the value, enabling efficient retrieval.
• Figure 4: The log of the walk-through example. The refined structure is marked in red, adding Miller compensation with a nulling resistor connected to the output ($\text{V}_{\text{out}}$).