HLS4PC: A Parametrizable Framework For Accelerating Point-Based 3D Point Cloud Models on FPGA

TL;DR

This work tackles real-time processing of sparse, unordered 3D point clouds for classification and segmentation by introducing HLS4PC, a parameterizable FPGA framework that uses fixed-point, streaming dataflow to accelerate point-based mapping and NN layers. It introduces PointMLP-Lite through hardware-aware compression (URS sampling, quantization, layer fusion, and input-point pruning), achieving roughly a 4x reduction in model complexity with about a 2% accuracy loss on ModelNet40. The authors demonstrate substantial throughput gains on a ZC706 FPGA platform—3.56x higher than prior FPGA work, and 2.3x and 22x faster than GPU and CPU baselines, respectively—highlighting practical benefits for safety-critical, real-time 3D perception. Together, the framework and compressed model offer flexible, high-throughput acceleration for evolving point cloud architectures on low-power hardware.

Abstract

Point-based 3D point cloud models employ computation and memory intensive mapping functions alongside NN layers for classification/segmentation, and are executed on server-grade GPUs. The sparse, and unstructured nature of 3D point cloud data leads to high memory and computational demand, hindering real-time performance in safety critical applications due to GPU under-utilization. To address this challenge, we present HLS4PC, a parameterizable HLS framework for FPGA acceleration. Our approach leverages FPGA parallelization and algorithmic optimizations to enable efficient fixed-point implementations of both mapping and NN functions. We explore several hardware-aware compression techniques on a state-of-the-art PointMLP-Elite model, including replacing FPS with URS, parameter quantization, layer fusion, and input-points pruning, yielding PointMLP-Lite, a 4x less complex variant with only 2% accuracy drop on ModelNet40. Secondly, we demonstrate that the FPGA acceleration of the PointMLP-Lite results in 3.56x higher throughput than previous works. Furthermore, our implementation achieves 2.3x and 22x higher throughput compared to the GPU and CPU implementations, respectively.

Figures (4)

• Figure 1: The HLS4PC framework workflow.
• Figure 2:
• Figure 3: Architecture of the convolution layer
• Figure 4: Pareto frontier illustrating OA vs. model size trade-off on the ModelNet40.