Simulating Circuit Layout for Distributed Quantum Computing

TL;DR

The paper tackles the scalability bottleneck of monolithic quantum processors by proposing distributed quantum computing (DQC) as a scalable alternative that leverages photonic interconnections between heterogeneous QPUs. It introduces an end-to-end automated layout compiler that follows a divide-and-conquer workflow—partitioning a circuit into subcircuits, performing backend-aware compilation on each QPU, and assembling a distributed layout using remote gate operations bridged by entangled pairs. The framework supports heterogeneity in QPU connectivity and gate sets, provides simulatable and implementable layouts, and demonstrates performance across GHZ, BitCode, TFIM, and QAOA benchmarks, showing near-ideal fidelity in noiseless simulations and clear overheads from inter-QPU communication. This work delivers a foundational validation platform for DQC strategies and a practical path toward benchmarking distributed circuit execution on future heterogeneous quantum networks.

Abstract

The proposed framework represents the first tool to compile a quantum circuit across photonic-connected distributed quantum processors. Its design follows a divide-and-conquer paradigm for circuit partitioning, transpilation, and assembly, producing simulable and implementable circuit layouts.

Figures (2)

• Figure 1: End-to-End Design Flow and Architecture of Our Framework.
• Figure 2: Example of Distributed Layout Compilation for GHZ6 Circuit using Our Framework.