Channel-last gate-all-around nanosheet oxide semiconductor transistors

Abstract

As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current ($>$ 1 mA/$μ$m) and low subthreshold swing (minimum of 63 mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.

Figures (6)

• Figure 1: Technology evolution with BEOL GAA transistors. (A) Technology‑node scaling has progressed from planar to FinFET to GAA to dense M3D integration with GAA. BEOL compatible AOS based self‑aligned GAA transistors are attractive for M3D because they can be vertically integrated into dense multilayer stacks with improved electrostatics. (B) In AOS‑based GAAsarkar2025first, traditionally the AOS channel is deposited first, followed by dielectric deposition directly on the channel (“channel‑first”). This process can damage the channel, adding additional oxygen vacancy donors thus, degrade device performance. Post‑deposition annealing is typically performed to recover the on/off ratio. However, it adds process complexity and can not fully recover the device metrices. Achieving high performance GAA with the traditional “channel-first” approach remains a central challenge. The proposed "channel last" (CL) GAA FET leverages a replacement‑channel concept that combines the benefits of BEOL‑compatible, back‑gated FETs and GAA architectures. This opens a path to M3D‑compatible GAA transistors built with ALD deposited any channel materials, such as AOS, 2D semiconductors.
• Figure 2: Channel-last gate-all-around field-effect transistor (CL GAA FET). The channel-last (CL) approach extends the channel-last advantages of back-gated FETs to GAA architectures. (A) Process flow of the CL GAA FET. A silicon dioxide (SiO2) nanosheet and a local back gate are deposited and patterned, after which a Ni anchor is formed to support the nanosheet. HF vapor selectively removes the SiO2 with near-infinite selectivity ($>$ 1000: 1) over Ni, creating a cavity that is sequentially filled by ALD, first with a hafnium oxide (HfO2) gate dielectric, then with an indium tungsten oxide AOS channel. (B) Cross sectional bright-field TEM image of the fabricated CL GAA FET. (C) Zoomed view of the cross-sectional TEM image. (D) HAADF STEM image showing the amorphous channel within the gate dielectric. (E)--(I) EDS elemental maps of the highlighted region, confirming that the AOS channel is surrounded by HfO2 dielectric, consistent with the channel-last GAA architecture.
• Figure 3: Electrical performance of CL GAA FETs. (A) A SEM image of a representative device structure and (B) an AFM image of IWO deposited on a control sample is showing uniform and smooth suface. (C) $I_\mathrm{D}$ versus $V_\mathrm{GS}$ characteristics for a CL GAA FET with $t_\mathrm{ch}$ = 6 nm measured at $V_\mathrm{DS} = 0.05~\text{V}$ and 1 V. (D) $I_\mathrm{D}$ versus $V_\mathrm{GS}$ characteristics for a CL GAA FET with $t_\mathrm{ch}$ = 9 nm, measured at $V_\mathrm{DS} = 0.05~\text{V}$ and 1 V. Dual sweep shows very low hysteresis of about 0.038 V at $V_\mathrm{DS} = 0.05~\text{V}$. (E) Extracted field‑effect mobility at $V_\mathrm{DS} = 0.05~\text{V}$. (F) Measured S.S. distribution showing a minimum value of 63.3 mV/dec, and an average over one decade is 65.9 mV/dec. (G) Output characteristics of $t_\mathrm{ch}$ = 9 nm device, showing a maximum current of 1 mA/µm at $V_\mathrm{DS} = 1~\text{V}$ and $V_\mathrm{GS} = 2~\text{V}$. (H) $I_\mathrm{D}$ versus $V_\mathrm{GS}$ for a CL GAA FET with a $t_\mathrm{ch}$ = 3 nm measured at $V_\mathrm{DS} = 0.05~\text{V}$ and 1 V.
• Figure 4: (I) Simulated electron density (cm-3) distribution in the nanosheet cross-section. As expected for a GAA geometry, the electron density is high along the entire nanosheet periphery in the on state and strongly suppressed in the off state, indicating uniform depletion. The simulation was calibrated to the measured transfer characteristics of a CL GAA FET with $t_\mathrm{ch}$= 9 nm under the same bias conditions. The map shown corresponds to representative on‑state and off-state conditions. (J) simulated and experimental $V_\mathrm{T}$ distribution shows reasonable agreement. $(\textbf{K}-\textbf{M})$ Benchmark analysis comparing the $I_\mathrm{on}$ (extracted at $V_\mathrm{DS} = 1~\text{V}$,$V_\mathrm{GS} = 2~\text{V}$), S.S., hysteresis and processing temperature, of AOS GAA, top‑gate, dual gate, with CL GAA FET (9 nm channel thickness). CL GAA FET achieves lower S.S., higher $I_\mathrm{on}$, , a lower hysteresis, and the lowest processing temperature.
• Figure 5: Indium oxide/hafnium oxide stack analysis. (A) HAADF-STEM image of IWO (low-Z-contrast)/HfO2 (high-Z-contrast) stack where HfO2 was deposited first on a blanket SiO2 substrate, followed by IWO (channel-last). The interface between IWO and HfO2 is sharp and clean (indicated by the guide arrow). (B) X-EDS elemental maps of O, Si, In, and Hf, confirming the expected composition and layer sequence. (C) High-resolution BF-STEM image along the SiO2 [110] zone axis with an inset FFT, showing the amorphous nature of the IWO layer. Selected regions of interest (ROIs) are indicated for FFT analysis. (D-E) FFTs from the ROIs in (C) exhibit diffuse amorphous rings without pronounced diffraction spots. The vertical streak originates from the BF-STEM scan direction. (F) HAADF-STEM images of a HfO2/IWO stack where IWO is deposited first on a blanket SiO2 substrate, followed by HfO2 deposition (channel-first). Some dark spots at the interface between IWO and HfO2 are observed (indicated by the guide arrow).