ElfCore: A 28nm Neural Processor Enabling Dynamic Structured Sparse Training and Online Self-Supervised Learning with Activity-Dependent Weight Update

TL;DR

ElfCore tackles the challenge of on-device learning for streaming event data by integrating a local online self-supervised learning engine, dynamic structured sparse training, and an activity-dependent weight update mechanism into a 28nm spiking neural network processor. The approach employs predictive and contrastive coding to enable multi-layer temporal learning without labels, and a sparse-to-sparse training regime with four N:M groups to prune and regrow connections efficiently. Hardware innovations include an asynchronous SerDes front-end, multi-timescale spike traces, and parallelized forward data paths that collectively reduce energy, memory, and latency while maintaining accuracy; end-to-end learning achieves substantial gains over state-of-the-art SNN accelerators. The resulting platform demonstrates strong applicability for edge sensing tasks (gesture, speech, biomedical signals) with up to 16x lower inference energy, 3.8x memory savings, and 5.9x higher network capacity efficiency, and is released as open-source for broader adoption and further development.

Abstract

In this paper, we present ElfCore, a 28nm digital spiking neural network processor tailored for event-driven sensory signal processing. ElfCore is the first to efficiently integrate: (1) a local online self-supervised learning engine that enables multi-layer temporal learning without labeled inputs; (2) a dynamic structured sparse training engine that supports high-accuracy sparse-to-sparse learning; and (3) an activity-dependent sparse weight update mechanism that selectively updates weights based solely on input activity and network dynamics. Demonstrated on tasks including gesture recognition, speech, and biomedical signal processing, ElfCore outperforms state-of-the-art solutions with up to 16X lower power consumption, 3.8X reduced on-chip memory requirements, and 5.9X greater network capacity efficiency.

Figures (8)

• Figure 1: Requirements for on-chip learning in processing streaming event data, highlighting three key challenges and their corresponding solutions.
• Figure 2: Chip architecture (top), neuron dynamics and similarity score logic (bottom left), and FSM (bottom right).
• Figure 3: Asynchronous de-serializer (top), asynchronous serializer (middle), and comparison with SoTA designs (bottom).
• Figure 4: On-chip learning: Enhanced OSSL with simultaneous PC and CC (top), and DSST employing sparse-to-sparse training (bottom).
• Figure 5: Enhanced efficiency in DSST: Avoids dense gradient sorting (top). The trade-off between acceleration and accuracy (middle). DSST restores accuracy (bottom).