Hardware-aware and Resource-efficient Circuit Packing and Scheduling on Trapped-Ion Quantum Computers

TL;DR

CircPack is presented, a hardware-aware circuit packing framework designed for modular trapped-ion devices based on the quantum charge-coupled device (QCCD) architecture that achieves up to 70.72% better fidelity, 62.67% higher utilization, and 32.80% improved layer reduction.

Abstract

The rapid expansion of quantum cloud services has led to long job queues due to single-tenant execution models that underutilize hardware resources. Quantum multi-programming (QMP) mitigates this by executing multiple circuits in parallel on a single device, but existing methods target superconducting systems with limited connectivity, high crosstalk, and lower gate fidelity. Trapped-ion architectures, with all-to-all connectivity, long coherence times, and high-fidelity mid-circuit measurement properties, presents itself as a more suitable platform for scalable QMP. We present CircPack, a hardware-aware circuit packing framework designed for modular trapped-ion devices based on the Quantum Charge-Coupled Device (QCCD) architecture. CircPack formulates static circuit scheduling as a two-dimensional packing problem with hardware-specific shuttling constraints. Compared to superconducting-based QMP approaches, CircPack achieves up to 70.72% better fidelity, 62.67% higher utilization, and 32.80% improved layer reduction. This framework is also capable of scalable, balanced scheduling across a cluster of independent QCCD modules, highlighting trapped-ion systems' potential in improving the throughput of quantum cloud computing in the near future.

Figures (7)

• Figure 1: A quantum circuit with a width of 2 qubits and depth of 5 layers.
• Figure 2: Quantum Multi-programming as performed on Superconducting circuit architectures (e.g., IBM-Q).
• Figure 3: (a) QCCD trapped ion modular system topology. (b) Gantt chart representation of a circuit schedule. (c) Example combined circuit with 2-qubit gates across 2 separate traps. (d) Trap-based packing method avoids shuttle operations.
• Figure 4: Fidelity vs 2-Qubit gate depth on random circuits using the MTS-QCCD and QCCDSim saki2022muzzlemurali2020architecting.
• Figure 5: An overview of the system comprised of the Circuit Scheduler and Execution Handler, along with the detailed Inputs and Outputs. First, (1) the circuits are preprocessed via native-gate compilation which are then (2) processed by the packing algorithm. Using the schedule generated from the packing, (3) the subcircuits are combined into a single QASM to be (4) sent for execution in the QPUs. Finally, (5) the result bitstrings are unbundled and the individual subcircuit fidelity results can be obtained.