Electrical Drive of a Josephson Junction Array using a Cryogenic BiCMOS Pulse Pattern Generator: Towards a Fully Integrated Josephson Arbitrary Waveform Synthesizer

TL;DR

The paper demonstrates the first co-integration of a Josephson junction array with a cryogenic BiCMOS pulse pattern generator to form a fully integrated Josephson arbitrary waveform synthesizer (JAWS). By combining a 16:1 serializer with a cryogenic clock distribution network and a modulator, the authors achieve data rates up to 30 Gb/s at 4 K and observe wide, well-defined Shapiro steps in JJA devices, validating the approach for ultra-low-noise quantum voltage generation. The work highlights robust timing alignment across 4 K to room temperature via Active Synchronization Lines and shows feasibility across different JJA sizes and measurement setups, marking a significant step toward scalable, low-noise quantum metrology and information systems. These results pave the way for a compact, integrated JAWS platform that minimizes cryogenic cabling and power, suitable for future quantum technologies.

Abstract

We combine a cryogenic BiCMOS integrated circuit, which generates high-speed return-to-zero (RTZ) pulses, with a superconducting Josephson junction array. The BiCMOS circuit acts as a cryogenic pulse pattern generator, delivering data rates of 30 Gb/s, while consuming 302 mW at 4 K. Each electrical pulse of the serializer effectively transfers one magnetic flux quantum through every Josephson junction, so that the average output voltage of the array produces well-defined plateaus (Shapiro steps) in its current-to-voltage characteristic. To the best of our knowledge, this is the first integration of a Josephson junction array with a cryogenic BiCMOS chip. The presented results pave the way toward a hybrid and fully integrated Josephson arbitrary waveform synthesizer (JAWS) that can generate ultra-low-noise signals for quantum voltage metrology and quantum information systems.

Figures (8)

• Figure 1: System realizations: (a) current PPG and 4K concept comparison, (b) Time diagram of the of JAWS operation: (1) serialized and modulated bit-sequence in PPG; (2) output of PPG or input for JAWS; (3) JAWS quantization; (4) JAWS output.
• Figure 2: Block diagram of the PPG.
• Figure 3: Synchronization issue: (a) 2:1 CML MUX, (b) aligned data and clocks signals, (c) misaligned data and clocks signals.
• Figure 4: 16:1 MUX realizations (a) 2:1 MUX based 16:1 MUX, (b) 8:1 MUX based 16:1 MUX.
• Figure 5: (a) 8:1 MUX schematic, (b) 12.5% clock generation.