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From the Two-Capacitor Paradox to Electromagnetic Side-Channel Mitigation in Digital Circuits

Raghvendra Pratap Singh, Baibhab Chatterjee, Shreyas Sen, Debayan Das

TL;DR

The paper addresses how energy lost during capacitor charging in CMOS contributes to EM side-channel leakage that enables key recovery. It uses RC and RLC circuit models to quantify the partition between heat and radiation, showing that $E_{\mathrm{heat}} + E_{\mathrm{rad}} = 0.5 C V_{DD}^2$. Key contributions include explicit expressions for energy distribution across RC, RLC, and parallel RC topologies and the identification of radiative losses as the exploitable leakage source. It advocates adiabatic charging as a viable mitigation, showing that increasing the charging time $T$ reduces radiative energy roughly as $E_{\mathrm{rad}} \propto 1/T^2$, enabling low-overhead EM SCA resilience. These results guide secure IC design by combining adiabatic charging with layout- and pre-silicon countermeasures to suppress EM leakage.

Abstract

The classical two-capacitor paradox of the lost energy is revisited from an electronic circuit security stand-point. The paradox has been solved previously by various researchers, and the energy lost during the charging of capacitors has been primarily attributed to the heat and radiation. We analytically prove this for various standard resistor-capacitor (RC) and resistor-inductor-capacitor (RLC) circuit models. From the perspective of electronic system security, electromagnetic (EM) side-channel analysis (SCA) has recently gained significant prominence with the growth of resource-constrained, internet connected devices. This article connects the energy lost due to capacitor charging to the EM SCA leakage in electronic devices, leading to the recovery of the secret encryption key embedded within the device. Finally, with an understanding of how lost energy relates to EM radiation, we propose adiabatic charging as a solution to minimize EM leakage, thereby paving the way towards low-overhead EM SCA resilience.

From the Two-Capacitor Paradox to Electromagnetic Side-Channel Mitigation in Digital Circuits

TL;DR

The paper addresses how energy lost during capacitor charging in CMOS contributes to EM side-channel leakage that enables key recovery. It uses RC and RLC circuit models to quantify the partition between heat and radiation, showing that . Key contributions include explicit expressions for energy distribution across RC, RLC, and parallel RC topologies and the identification of radiative losses as the exploitable leakage source. It advocates adiabatic charging as a viable mitigation, showing that increasing the charging time reduces radiative energy roughly as , enabling low-overhead EM SCA resilience. These results guide secure IC design by combining adiabatic charging with layout- and pre-silicon countermeasures to suppress EM leakage.

Abstract

The classical two-capacitor paradox of the lost energy is revisited from an electronic circuit security stand-point. The paradox has been solved previously by various researchers, and the energy lost during the charging of capacitors has been primarily attributed to the heat and radiation. We analytically prove this for various standard resistor-capacitor (RC) and resistor-inductor-capacitor (RLC) circuit models. From the perspective of electronic system security, electromagnetic (EM) side-channel analysis (SCA) has recently gained significant prominence with the growth of resource-constrained, internet connected devices. This article connects the energy lost due to capacitor charging to the EM SCA leakage in electronic devices, leading to the recovery of the secret encryption key embedded within the device. Finally, with an understanding of how lost energy relates to EM radiation, we propose adiabatic charging as a solution to minimize EM leakage, thereby paving the way towards low-overhead EM SCA resilience.
Paper Structure (8 sections, 7 equations, 4 figures)

This paper contains 8 sections, 7 equations, 4 figures.

Table of Contents

  1. Introduction
  2. Related Work
  3. Analysis of the Lost Energy During Capacitor Charging
  4. Heat Dissipation in the Standard RC Model
  5. EM Radiation During Capacitor Charging
  6. Energy Loss Distribution Across Different Circuit Models
  7. Minimizing the EM Radiation for EM SCA Attack Resilience
  8. Conclusion and Future Work

Figures (4)

  • Figure 1: Transistor circuits like CMOS inverter operation during signal transitions. When the input switches, either the PMOS or the NMOS conducts, causing the load capacitor $C$ to charge or discharge. The resulting transient current leads to energy dissipation through heat and EM radiation.
  • Figure 2: EM SCA on an 8-bit Microcontroller: (a) Automated 3D scanning system with H-field probe and amplifier, (b) Heatmap of signal amplitude, (c) SNR map highlighting regions of strong EM leakage, and (d) MTD indicating regions with the highest data-dependent leakage danial2020scniffer.
  • Figure 3: Energy lost as heat ($E_{\text{heat}}$, red) and radiation ($E_{\text{rad}}$, blue) versus resistance $R$. Left to right: (a) Series RLC circuit, (b) Series RC circuit, and (c) Parallel RC circuit; respective energy plots are shown in (d), (e), and (f) plots. The figure illustrates how energy dissipation transitions from radiative to resistive loss as $R$ varies across different circuit configurations.
  • Figure 4: Energy lost as heat and normalized EM radiation vs. charging time (log scale). As charging slows, energy losses approach zero, confirming that adiabatic charging suppresses EM side-channel leakage by reducing voltage transition rates.