Pyroelectric effects in hybrid semiconductor-lithium niobate quantum devices

Abstract

Hybrid quantum devices using surface acoustic waves show promise as key elements of quantum information processors. We report measurements of integrated flip-chip devices consisting of semiconductor quantum dots and surface acoustic wave resonators in lithium niobate. We observed that the pyroelectric effect in lithium niobate inhibited the operation of quantum dots in the integrated devices. GaAs/AlGaAs devices suffered from unintentional carrier depletion, and Si/SiGe devices suffered from electrostatic discharge. Our results highlight the importance of mitigating pyroelectric effects in semiconductor-lithium niobate hybrid devices for continued progress in quantum interconnects and transducers.

Figures (7)

• Figure 1: Electrical schematic of a capacitively coupled DQD - SAW flip-chip device, corresponding to the QD devices fabricated in this work. The capacitances determining the effective coupling are the feed-line capacitance to the gate electrode C$_{FL}$, the inter substrate flip-chip capacitance C$_{FC}$ and the IDT capacitance C$_{IDT}$. The DQD system is realized either in GaAs/AlGaAs or Si/SiGe, whereas the SAW resonator is fabricated on a LN substrate.
• Figure 2: (a) SEM image of a depletion mode DQD fabricated on a GaAs/AlGaAs heterostructure in a stadium-style geometry. (b) SEM image of an accumulation mode DQD fabricated on a Si/SiGe heterostructure in an overlapping-gate geometry. (c) Optical image of a SAW resonator fabricated on a LN substrate. (d) Optical image of an assembled GaAs/AlGaAs-LN flip-chip device. The white rectangle highlights the region in which the mesa containing the DQD is located.
• Figure 3: (a) Optical image of a DQD structure on a GaAs/AlGaAs substrate depicting the ohmic contacts. In an integrated flip-chip device, the LN chip would be above this image, as indicated by the white arrow. The inset shows an SEM image of the small gate electrodes. (b) Temperature dependence of the current between two ohmics is shown for devices D2, D3, and D4. Black curves are the response of the full flip-chip device, and the red curves are for the devices without the LN chip. (c) Current between ohmic contacts O1 and O2 of D1 plotted as a function of the voltage applied to all the gates shown in (a). (d) Current between ohmic contacts O1 and O2 of device D3 plotted as a function of the voltage applied to the gate electrodes mentioned in the legends.
• Figure 4: (a) Optical image of Si/SiGe-LN device D5 in which a blank LN chip is glued near a field effect transistor. (b) The source-drain current measured at 4 K is plotted as a function of the gate voltage for D5 with and without LN. (c, d) Optical images of the gates on Si/SiGe device D6 before and after cool down, respectively. (e, f) Optical image of the IDTs on the LN substrate of device D6 before and after cooldown, respectively.
• Figure 5: (a) Schematic of the measurement circuit used to measure voltage differences between the two LN planes. (b) Measured voltage and temperature are shown as a function of time while cooling down and warming up. (c-d) Schematic of the measurement circuit used to measure in-plane potential differences and corresponding measured voltage and temperature while cooling down and warming up. (e-f) Schematic of the measurement circuit for one-side aluminum-coated LN and corresponding measured voltage and temperature while cooling down and warming up. The vertical dashed line in (b,d,f) marks the beginning of warm-up.