Phantom LAM and LLI: Resistance and Hysteresis Bias in Voltage-Curve Degradation Mode Analysis

TL;DR

The paper identifies two key non-degradation sources in voltage-curve degradation-mode analysis (DMA): SOC-dependent ohmic drop and intrinsic voltage hysteresis, which can produce phantom LAM/LLI when DMA is applied to pseudo-OCV traces. It introduces an instantaneous ohmic resistance measure $R_\Omega( ext{SOC})$ from ~50 ms pulses to perform an IR correction and analyzes hysteresis as an inherent thermodynamic property, emphasizing the need for window harmonization and careful branch choice. Using two commercial 21700 cells (LG M50T and Molicel P45B) with a fixed 2.5–4.2 V window, the study demonstrates that uncorrected IR effects can misallocate degradation (e.g., underestimating PE-LAM and LLI, overestimating graphite LAM; and hysteresis-driven biases between charge vs discharge branches). The authors propose a practical protocol: apply ohmic-only correction, harmonize the voltage window, and base quantitative DMA on the discharge branch to obtain robust degradation attributions, particularly isolating Si-driven loss in Gr/SiOx anodes. This approach improves the reliability of DMA across chemistries and supports more accurate material-dissipation assessments in battery diagnostics.

Abstract

Degradation mode analysis (DMA) is widely used to decompose capacity fade into loss of lithium inventory (LLI) and loss of active material (LAM) from low-rate voltage-capacity data. Yet the measured trace is a pseudo-OCV (pOCV) that includes two non-degradation contributions: an SOC-dependent ohmic drop and intrinsic charge-discharge hysteresis, especially in graphite--silicon oxide (C/SiOx) negative electrodes. We show these can dominate attribution and generate Phantom LAM/LLI --apparent material loss created by curve registration, branch choice and voltage-windowing rather than true degradation. Using two commercial 21700 cells (LG M50T: higher resistance; Molicel P45B: lower resistance), we extract an SOC-dependent instantaneous resistance $R_Ω(\mathrm{SOC})$ from the first $\sim$50,ms pulse step and apply an IR correction to pOCV before fitting. In LG M50T, IR correction lifts the low-rate discharge pOCV by $+13$--$27$,mV with ageing; without it, PE-LAM is increasingly under-diagnosed (to $-8.80%$ relative error at late life) and LLI is suppressed (median $-3.07%$), with compensating inflation of apparent graphite loss. In P45B, on a branch-fair $3.0$--$4.2$,V window, end-of-life charge-branch DMA reports higher PE-LAM ($+3.42$,pp) and LLI ($+5.36$,pp), while the discharge branch recovers larger Si-LAM (discharge--charge difference to $+14.38$,pp). Raising the lower cutoff ($2.5$--$4.2 \rightarrow 3.0$--$4.2$,V) further under-reports Si-LAM by $13.61$,pp by removing the Si-sensitive low-voltage tail. We propose a practical protocol: correct only the instantaneous ohmic term, harmonize the voltage window, and base quantitative attribution on the discharge branch, treating anomalous/negative component LAMs on charge as allocation artefacts rather than recovery.

Figures (9)

• Figure 1: LG M50T resistance evolution during discharge. Instantaneous resistance versus SoC and throughput. Marker color encodes total resistance ($m\Omega$); larger markers at high SoC and late life highlight the SoC-dependent growth. SoH at each RPT is shown above the columns.
• Figure 2: Low-rate signatures before/after IR correction. (a) V–Q: IR correction lifts the curve (blue: first cycle; red: last; dashed = original pOCV, solid = pOCV+IR). (b) dV/dQ–Q: small shape changes; slight spread compaction. (c) dQ/dV–V: consistent right-shifts of peaks/valleys with conserved area (capacity).
• Figure 3: Resistance map (P45B). Instantaneous resistance at $\approx$30, 50, 70 % SoC across RPTs (SoH $\approx$ 1.00, 0.98, 0.96, 0.93). Points cluster narrowly around 23–26 $m\Omega$ with minimal aging drift, substantially below LG M50T at comparable SoH.
• Figure 4: (a) Low-rate pOCV overlays. Charge (dashed) and discharge (solid) for first and last RPT. The charge trace begins above 2.5 V (non-zero initial SoC) due to relaxation; a common lower-voltage limit is used for fair branch comparison. Separation is smallest near mid-SoC and larger toward both ends. (b) Hysteresis distribution by SoC. Absolute area between branches integrated in 5 %-SoC windows. Low-SoC contracts, high-SoC grows slightly, and the total over the common window increases marginally.
• Figure 5: Impact of resistance on DMA-emergence of phantom LAM (LG M50T, 25 ° C, discharge pOCV).Panels show absolute mode values (left axis; Original dashed, IR-corrected solid) and the relative error of the uncorrected estimate with respect to the corrected one (bars, right axis); throughput capacity (Ah) is on the x-axis. (a) SoH; (b) $LAM_{PE}$; (c) $LLI$; (d) $LAM_{NE}$; (e) $LAM_{Gr}$; (f) $LAM_{Si}$