Low-Latency and Low-Complexity MLSE for Short-Reach Optical Interconnects

TL;DR

This work tackles the need for high-speed, low-latency, and low-complexity sequence detection in short-reach optical interconnects by introducing a simplified MLSE that merges computational simplification with reduced-state MLSE. A parallel sliding-block architecture yields latency on the order of $O(\log N)$ with linear growth in multipliers, while maintaining BER performance comparable to full MLSE. The authors provide detailed architectural analyses, including 1S-MLSE, low-latency MLSE, and two levels of simplification, with concrete complexity reductions: variable multipliers drop from exponential to linear in $N$, and adders/comparators shrink substantially. Experimental validation at 112-Gb/s PAM4 over 2-km SSMF shows the simplified MLSE achieving the 7% FEC BER limit at $\text{ROP}=-7.5$ dBm, while reducing latency from 34 to 7 delay units and lowering hardware resources by large factors, offering a practical path toward high-speed, low-latency optical interconnects.

Abstract

To meet the high-speed, low-latency, and low-complexity demand for optical interconnects, simplified maximum likelihood sequence estimation (MLSE) is proposed in this paper. Simplified MLSE combines computational simplification and reduced state in MLSE. MLSE with a parallel sliding block architecture reduces latency from linear order to logarithmic order. Computational simplification reduces the number of multipliers from exponential order to linear order. Incorporating the reduced state with computational simplification further decreases the number of adders and comparators. The simplified MLSE is evaluated in a 112-Gbit/s PAM4 transmission over 2-km standard single-mode fiber. Experimental results show that the simplified MLSE significantly outperforms the FFE-only case in bit error ratio (BER) performance. Compared with simplified 1-step MLSE, the latency of simplified MLSE is reduced from 34 delay units in linear order to 7 delay units in logarithmic order. The simplified scheme in MLSE reduces the number of variable multipliers from 512 in exponential order to 33 in linear order without BER performance deterioration, while reducing the number of adders and comparators to 37.2% and 8.4%, respectively, with nearly identical BER performance.