Shuttling Compiler for Trapped-Ion Quantum Computers Based on Large Language Models

TL;DR

The paper introduces a layout-independent shuttling compiler for trapped-ion quantum computers, leveraging fine-tuned large language models to generate hardware-level shuttling sequences. It proposes a three-phase pipeline (dataset generation in Alpaca format, Axolotl-based fine-tuning, and vLLM-based inference) and demonstrates results on linear and branched 1D trap architectures, with partial success on unseen layouts. While some small circuits see improved shuttling efficiency over classical compilers, robustness and generalization decline as circuit size grows, underscoring the need for advanced training strategies like direct preference optimization and reinforcement learning with human feedback. Overall, the work establishes a foundational step toward flexible, architecture-agnostic shuttling software for trapped-ion devices and outlines concrete paths for improving performance and generalization.

Abstract

Trapped-ion quantum computers based on segmented traps rely on shuttling operations to establish connectivity between multiple sub-registers within a quantum processing unit. Several architectures of increasing complexity have already been realized, including linear arrays, racetrack loops, and junction-based layouts. As hardware capabilities advance, the need arises for flexible software layers within the control stack to manage qubit routing$\unicode{x2014}$the process of dynamically reconfiguring qubit positions so that all qubits involved in a gate operation are co-located within the same segment. Existing approaches typically employ architecture-specific heuristics, which become impractical as system complexity grows. To address this challenge, we propose a layout-independent compilation strategy based on large language models (LLMs). Specifically, we fine-tune pretrained LLMs to generate the required shuttling operations. We evaluate this approach on both linear and branched one-dimensional architectures, demonstrating that it provides a foundation for developing LLM-based shuttling compilers for trapped-ion quantum computers.

Figures (5)

• Figure 1: Overview of the three phases of our compiler. We first generate training and evaluation datasets in Alpaca format, where each entry consists of an instruction and its corresponding output. These datasets are then used to fine-tune an LLM with Axolotl, which involves pre-processing and training. Finally, the fine-tuned model is deployed for inference to compute shuttling schedules by submitting instructions to a vLLM server.
• Figure 2: Shuttling schedule of a quantum circuit with two qubits and three gates on a linear architecture consisting of three segments. Both qubits are initially located in gate segment $1$. The lines indicate the qubit movements between the segments, while the purple dots denote gate executions. The executed shuttling operations are annotated alongside the lines. For dataset generation, the complete shuttling schedule is decomposed into multiple data entries, where each entry contains the shuttling operations between two consecutive gate executions, as indicated by the dotted lines.
• Figure 3: Graph representations of ion-trap architectures. Red vertices denote gate segments (GS), yellow vertices denote storage segments, and green vertices denote junctions, which are the only vertices connected to more than two others. Numbers serve as unique vertex identifiers.
• Figure 4: Quantum circuit with four qubits and 14 gates. Purple gates form the first layer and are executable when their qubits are located in a gate segment, whereas yellow gates belong to deeper layers and are not yet executable. For each qubit, gates are numbered in ascending order to indicate their execution sequence.
• Figure 5: Graph representations of ion-trap architectures used to evaluate the generalization capabilities of the fine-tuned LLMs on previously unseen layouts. Architectures (a) and (b) feature three-way junctions, while architecture (c) contains four-way junctions. For each layout, the number of yellow storage vertices was scaled to match the qubit count of the respective test circuit.