First results of a Monolithic Active Pixel Sensor with Internal Signal Gain Fully Integrated in a 180 nm CMOS Technology

TL;DR

The paper demonstrates the first results of the CASSIA sensor, a monolithic MAPS with in-pixel internal amplification implemented in a TowerSemiconductor 180 nm process. By integrating DP and XDP gain layers under the central n$^{+}$ electrode, the authors realize both LGAD-like low-gain and SPAD-like high-gain operation within a single device, tunable by bias voltage. DC and optical measurements show controllable gain onset ($V_{LGAD}$) and breakdown ($V_{BR}$), with gains spanning up to >$10^{3}$–$10^{6}$ in different modes and configurations, and DCRs as low as ≈0.01 Hz/μm$^{2}$ at room temperature for optimized designs. The work demonstrates uniform avalanche gain distributions across active areas and preserves device simplicity by using standard process layers, underscoring the potential for large-scale, timing-capable 4D tracking in future high-energy physics experiments.

Abstract

Dense tracking environments in experiments at CERN's High-Luminosity LHC and future FCC experiments call for an increased use of timing information in addition to the position measurement of pixel detectors. This adds one dimension to the information available, and is essential for pile-up mitigation at high luminosity. The CASSIA sensor project (CMOS Active SenSor with Internal Amplification) focuses on the development of pixel matrices with internal charge multiplication based on monolithic CMOS sensor technologies suitable for application as charged particle tracking and timing detectors. CMOS sensors with in-pixel internal amplification would result in higher signal amplitudes having an improved signal-to-noise ratio, better time resolution and increased sensitivity, making them attractive for high-radiation environments. Their monolithic integration in small pixels reduces the input capacitance of a front-end amplifier and power dissipation making it suitable for fine-pitch low-power detectors. Fast signal rise time due to internal charge amplification improves the response time and timing resolution, all of which makes such a technology attractive for future 4D tracking applications in HEP experiments. This paper presents the first results of the CASSIA sensor, a novel MAPS which uses gain layers fully integrated in a 180nm imaging process to achieve internal signal amplification. In the first measurements presented here we demonstrate the gain behaviour of different pixel implant designs and show that the sensor can be operated with low gain proportional mode as LGAD sensor at lower voltages and as SPAD sensor at higher voltages.

Figures (23)

• Figure 1: Cross section of CASSIA sensors: Sensor M1 (a) with standard n$^{+}$-electrode without gain layer, Sensor M2/S4/S5 (b) with a deep p-well (DP) gain layer, Sensor M3/S6 (c) with a extra deep p-well (XDP) gain layer, Sensor M4/S19 (d) with a extra deep p-well gain layer and shallow n$^{+}$-electrode implant and Sensor S13/S4 with a deep n$^{+}$-electrode and extra deep p-well (XDP) gain layer.
• Figure 2: The CASSIA-1 chip, containing 24 single pixels and four 3x3 matrices.
• Figure 3: TCAD simulated IV curve for matrix M1 (black) without gain layer, M2 (red) with a deep p-well (DP) gain layer, M3 (blue) with a extra deep p-well (XDP) gain layer, M4 (green) with a extra deep p-well (XDP) gain layer and shallow n$^{+}$-electrode. Solid curves show current from the n$^{+}$-electrode to substrate; dashed curves show current from the n$^{+}$-electrode to the electronics p-well.
• Figure 4: Right half of CASSIA structure showing generic TCAD simulations of electric field distribution at 55 V: (a) Matrix M2 with deep p-well (DP) gain layer of 20 $\mu$m diameter and (b) Matrix M3 with extra deep p-well (XDP) gain layer of 12 $\mu$m diameter.
• Figure 5: Generic TCAD simulations of avalanche multiplication (impact ionization) rate distribution in CASSIA with 8 $\upmu$m n$^{+}$-electrode to electronics p-well spacing: (a) Matrix M2 with DP gain layer biased at 56 V, (b) Matrix M3 with XDP gain layer biased at 103 V.