LLM-based Behaviour Driven Development for Hardware Design

TL;DR

Problem: complexity of verification in hardware design makes manual creation of BDD scenarios error-prone. The authors present an LLM-driven workflow that converts plain textual specifications into both synthesizable Verilog and Gherkin-based BDD scenarios, using a minimal prompting setup and a local template engine. They demonstrate the approach on a 16-bit ALU, producing an executable Verilog model and automatically generated test scenarios that are verifiable via Verilog simulation and GTKWave. The results indicate substantial potential to reduce manual effort and improve consistency across specification, implementation, and verification, paving the way for more automated, specification-driven hardware development.

Abstract

Test and verification are essential activities in hardware and system design, but their complexity grows significantly with increasing system sizes. While Behavior Driven Development (BDD) has proven effective in software engineering, it is not yet well established in hardware design, and its practical use remains limited. One contributing factor is the manual effort required to derive precise behavioral scenarios from textual specifications. Recent advances in Large Language Models (LLMs) offer new opportunities to automate this step. In this paper, we investigate the use of LLM-based techniques to support BDD in the context of hardware design.

Figures (4)

• Figure 1: Automatically generated scenario for the ADD operation
• Figure 2: Development environment
• Figure 3: Simulation of a generated scenario on the Verilog
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