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SPIDER, a Waveform Digitizer ASIC for picosecond timing in LHCb PicoCal

Ludovic Alvado, Nicolas Arveuf, Edouard Bechetoille, Guillaume Blanchard, Dominique Breton, Baptiste Joly, Laurent Leterrier, Jihane Maalmi, Samuel Manen, Hervé Mathez, Christophe Sylvia, Philippe Vallerand, Richard Vandaele

TL;DR

SPIDER targets sub-15 ps timing precision for LHCb PicoCal by implementing a Waveform Time-to-Digital Converter in a 65 nm CMOS ASIC. The design uses two DLLs to define phase-locked sampling windows and a 32-sample analog memory per channel feeding a 10-bit Wilkinson ADC at up to 5 GHz, enabling precise time reconstruction of waveforms with low latency. Early results show ~850 mV dynamic range, ~±0.2% linearity, ~1 mV rms noise, and timing resolutions down to several picoseconds, with ongoing work to address PLL lock and crosstalk; an 8-channel SPIDER_V0+ variant is planned to scale occupancy and channel count for PicoCal and other fast detectors.

Abstract

We present the architecture, design and first test results of SPIDER, the first prototype of a TSMC CMOS 65 nm ASIC designed for the time measurement path of LHCb Electromagnetic Calorimeter after LS4 Upgrade. The main requirements for the readout of this detector are a time resolution below 15 ps rms above 5 GeV, and a channel occupancy up to 30\% (12 Mevent/s). The first prototype called SPIDER\_V0 is a 2-channel waveform digitizer locked on the LHC clock allowing precise time reconstruction by digital algorithms. The architecture is based on 2 DLLs in series controlling respectively the phase of the sampling window and the sampling frequency, the latter covering the range between 2 and 20 GS/s. Each self-triggering channel houses 8 banks of 32 analog memory cells and a massively parallel Wilkinson ADC for conversion at 5 GHz over 10 bits with a maximal conversion time of 200 ns. SPIDER targets not only LHCb, but all fast detectors mounted on current and future accelerators. Its sampling frequency can indeed be adjusted to different signal risetimes. Its main frequency of 40 MHz could even be eventually locked to another value by modifying only one of the DLLs in the chip design.

SPIDER, a Waveform Digitizer ASIC for picosecond timing in LHCb PicoCal

TL;DR

SPIDER targets sub-15 ps timing precision for LHCb PicoCal by implementing a Waveform Time-to-Digital Converter in a 65 nm CMOS ASIC. The design uses two DLLs to define phase-locked sampling windows and a 32-sample analog memory per channel feeding a 10-bit Wilkinson ADC at up to 5 GHz, enabling precise time reconstruction of waveforms with low latency. Early results show ~850 mV dynamic range, ~±0.2% linearity, ~1 mV rms noise, and timing resolutions down to several picoseconds, with ongoing work to address PLL lock and crosstalk; an 8-channel SPIDER_V0+ variant is planned to scale occupancy and channel count for PicoCal and other fast detectors.

Abstract

We present the architecture, design and first test results of SPIDER, the first prototype of a TSMC CMOS 65 nm ASIC designed for the time measurement path of LHCb Electromagnetic Calorimeter after LS4 Upgrade. The main requirements for the readout of this detector are a time resolution below 15 ps rms above 5 GeV, and a channel occupancy up to 30\% (12 Mevent/s). The first prototype called SPIDER\_V0 is a 2-channel waveform digitizer locked on the LHC clock allowing precise time reconstruction by digital algorithms. The architecture is based on 2 DLLs in series controlling respectively the phase of the sampling window and the sampling frequency, the latter covering the range between 2 and 20 GS/s. Each self-triggering channel houses 8 banks of 32 analog memory cells and a massively parallel Wilkinson ADC for conversion at 5 GHz over 10 bits with a maximal conversion time of 200 ns. SPIDER targets not only LHCb, but all fast detectors mounted on current and future accelerators. Its sampling frequency can indeed be adjusted to different signal risetimes. Its main frequency of 40 MHz could even be eventually locked to another value by modifying only one of the DLLs in the chip design.

Paper Structure

This paper contains 3 sections, 7 figures.

Table of Contents

  1. The upgrade of LHCb calorimeter
  2. The SPIDER ASIC
  3. Test benches and first results

Figures (7)

  • Figure 1: Left: SpaCal (top) and Shashlik (bottom) dual readout modules; right: block diagram of PicoCal electronics chain.
  • Figure 2: Left: principle of Waveform TDC. Right: chronogram of sampling, trigger and conversion in SPIDER.
  • Figure 3: SPIDER_V0 functional block diagram.
  • Figure 4: Test benches in LPCA (left) and IJCLab (middle). SPIDER_V0 layout (right).
  • Figure 5: ADC calibration (left). Residuals after linear fit in % (middle) and intercept in mV (right).
  • ...and 2 more figures