From Liability to Asset: A Three-Mode Grid-Forming Control Framework for Centralized Data Center UPS Systems

TL;DR

<3-5 sentence high-level summary> The paper addresses stability challenges posed by large data-center loads at weak-grid interconnections by proposing a centralized medium-voltage UPS with a three-mode supervisory framework. Mode 1 ensures internal continuity via a DC-stiff bus, Mode 2 delivers fault resilience through active/reactive power decoupling with UPS-BESS buffering and a rate-limited soft return, and Mode 3 provides optional droop-based fast frequency response. Fundamental-frequency averaged-dq simulations show that Mode 2 reduces peak inverter current, preserves IT energy, and improves PCC voltage during faults compared with grid-following baselines, while Mode 1 stabilizes the DC link and Mode 3 offers bulk-frequency support. The approach offers a scalable mechanism to maintain IT continuity, mitigate grid impacts, and enable grid-support functionality, with EMT/HIL validation identified as future work.

Abstract

AI workloads are turning large data centers into highly dynamic power-electronic loads; fault-time behavior and workload pulsing can stress weak-grid points of interconnection. This paper proposes a centralized medium-voltage (MV) uninterruptible power supply (UPS) control architecture implemented as three operating modes: Mode 1 regulates a DC stiff bus and shapes normal-operation grid draw, Mode 2 enforces current-limited fault-mode P--Q priority with UPS battery energy storage system (UPS-BESS) buffering and a rate-limited post-fault "soft return," and Mode 3 optionally provides droop-based fast frequency response via grid-draw modulation. Fundamental-frequency averaged dq simulations (50 MW block, short-circuit ratio (SCR) = 1.5, 0.5 p.u. three-phase dip for 150~ms) show zero unserved information-technology (IT) energy (0.00000 MWh vs.0.00208 MWh for a momentary-cessation benchmark), a 0.57 p.u. peak inverter current (vs. 1.02 p.u. for a synchronous-reference-frame phase-locked loop (SRF-PLL) low-voltage ride-through (LVRT) baseline), a nonzero mean fault-window grid draw of 0.20~p.u. (vs.approx 0 for momentary cessation), and an improved settled point-of-common-coupling (PCC) voltage minimum of 0.79 p.u. after one cycle (vs. 0.66 p.u.). A forced-oscillation case study applies a 1 Hz pulsed load (+/- 0.25 p.u.) and shows that the normal-operation shaping filters the oscillation seen by the grid while the UPS-BESS buffers the pulsing component.

Figures (6)

• Figure 1: High-level block diagram of the averaged control structure implemented in simulation. Mode switching is represented explicitly as a switch/multiplexer: Mode 2 preempts Modes 1/3 during fault/low-voltage conditions by selecting the fault setpoint path (current-limited P--Q priority), while normal operation selects the Mode 1/3 setpoint path (DC stiff bus with optional droop/FFR). The selected setpoints drive a common outer-loop chain with rate-limited recovery, and the UPS-BESS buffers the resulting active-power mismatch within constraints.
• Figure 2: Mode 1 normal-operation power shaping: (a) the ramping behavior is an intentional choice from the grid-draw shaping block (finite $\tau_{grid}$) under a step in IT load, and (b) under a 1 Hz pulsed load the UPS-BESS buffers the high-frequency component, reducing the oscillatory active power seen by the grid.
• Figure 3: Mode 1 (DC stiff bus) demonstration under a no-fault pulsed-load scenario with an initial DC-link energy deficit ($V_{dc}(0)<V_{dc,ref}$): comparison of $V_{dc}$, $P_{bess}$, and SoC with Mode 1 disabled vs enabled. The shaded window indicates the pulsed-load interval.
• Figure 4: Averaged $dq$ simulation results comparing two GFL baselines to the proposed Mode 2 controller: GFL with momentary cessation (red), GFL with SRF-PLL and LVRT reactive priority (magenta), and proposed controller (blue). The three-phase voltage dip is applied from $t=0.50$ s to $t=0.65$ s (yellow band). Panels show (a) active power drawn from the grid (IT load shown as reference; dotted line indicates the minimum-draw policy $P_{draw,min}^{fault}$), (b) $|V_{pcc}|$, (c) $dq$ currents under a vector current limit (with $i_d<0$ indicating net grid draw under the adopted sign convention), and (d) DC-link proxy voltage $V_{dc}$.
• Figure 5: Comparison of averaged-$dq$ and EMT-style fixed-step $abc$ simulation for the proposed controller (non-switching, commanded-voltage VSC). To allow a settled pre-fault operating point in both models, the voltage dip is applied later in the window (yellow band, $t=6.0$--$6.15$ s). For apples-to-apples comparison, the EMT traces are post-processed into the same phasor-equivalent Thevenin PCC quantities used in the averaged model. Panels show (top) $P_{draw}$, (middle) $|V_{pcc}|$, (bottom) $|I|$. While startup and recovery match, the fault window reveals that the averaged model is conservative, predicting voltage collapse under the quasi-static algebraic grid constraint. In contrast, the EMT dynamics (specifically grid inductance) physically constrain the rate of voltage decay, allowing the fast controller to intervene and maintain stability. This confirms the averaged model as a safe, lower-bound design tool.