Surrogate Neural Architecture Codesign Package (SNAC-Pack)

TL;DR

NAS often relies on proxies that poorly reflect hardware performance, hindering FPGA deployment. SNAC-Pack fuses NAC with a surrogate resource estimator to enable hardware-aware multi-objective NAS, balancing accuracy, FPGA resource use, and latency without exhaustive synthesis. On a jet-classification task, SNAC-Pack achieves competitive accuracy and resource profiles, with potential latency improvements after synthesis. The work provides an open-source FPGA-oriented NAS toolkit and highlights avenues to further refine surrogate models for tighter hardware performance guarantees.

Abstract

Neural Architecture Search is a powerful approach for automating model design, but existing methods struggle to accurately optimize for real hardware performance, often relying on proxy metrics such as bit operations. We present Surrogate Neural Architecture Codesign Package (SNAC-Pack), an integrated framework that automates the discovery and optimization of neural networks focusing on FPGA deployment. SNAC-Pack combines Neural Architecture Codesign's multi-stage search capabilities with the Resource Utilization and Latency Estimator, enabling multi-objective optimization across accuracy, FPGA resource utilization, and latency without requiring time-intensive synthesis for each candidate model. We demonstrate SNAC-Pack on a high energy physics jet classification task, achieving 63.84% accuracy with resource estimation. When synthesized on a Xilinx Virtex UltraScale+ VU13P FPGA, the SNAC-Pack model matches baseline accuracy while maintaining comparable resource utilization to models optimized using traditional BOPs metrics. This work demonstrates the potential of hardware-aware neural architecture search for resource-constrained deployments and provides an open-source framework for automating the design of efficient FPGA-accelerated models.

Figures (4)

• Figure 1: SNAC-Pack Pareto front of estimated average resources versus estimated clock cycles. Each point represents a unique architecture sampled.
• Figure 2: SNAC-Pack Pareto fronts of estimated average resources versus accuracy. Each point represents a unique architecture sampled.
• Figure 3: SNAC-Pack Pareto fronts of estimated clock cycles versus accuracy. Each point represents a unique architecture sampled.
• Figure 4: NAC Pareto front of BOPs versus accuracy. Each point represents a unique architecture sampled.