Logo
ScienceStack
Table of Contents
Fetching ...
Sign In

Enabling Technologies for Scalable Superconducting Quantum Computing

Xanthe Croot, Kasra Nowrouzi, Christopher Spitzer, Carmen G. Almudever, Alexandre Blais, Malcolm Carroll, Jerry Chow, Daniel Friedman, Masao Tokunari, Edoardo Charbon, Vivek Chidambaram, Andrew N. Cleland, David Danovitch, Joseph Emerson, David Gunnarsson, Raymond Laflamme, John Martinis, Robert McDermott, William D. Oliver, Michel Pioro-Ladriere, Yoshiaki Sato, Hidenori Ohata, Kouichi Semba, Irfan Siddiqi

TL;DR

This roadmap identifies the critical technological frontiers needed to scale superconducting quantum computers beyond a handful of qubits into fault-tolerant architectures. It argues for modular QPU designs, scalable cryogenic and cryogenic-electronic infrastructure, and integrated control and software stacks, all supported by standardized testbeds and industry-focused foundry models. Key contributions include a structured set of design considerations across modules, cryogenics, wiring, electronics, control, calibration, error suppression/correction/mitigation, and verification, along with recommendations for ecosystem-building and workforce development. The practical impact is a coordinated, multi-institutional path toward scalable, reliable quantum processors capable of supporting FTQC with manageable cost and maintainability.

Abstract

Experiments with superconducting quantum processors have successfully demonstrated the basic functions needed for quantum computation and evidence of utility, albeit without a sizable array of error-corrected qubits. The realization of the full potential of quantum computing centers on achieving large scale fault-tolerant quantum computers. Science, engineering and industry advances are needed to robustly generate, sustain, and efficiently manipulate an exponentially large computational (Hilbert) space as well as supply the number and quality components needed for such a scaled system. In this article, we suggest critical areas of quantum system and ecosystem development, with respect to the handling and transmission of quantum information within and out of a cryogenic environment, that would accelerate the development of quantum computers based on superconducting circuits.

Enabling Technologies for Scalable Superconducting Quantum Computing

TL;DR

This roadmap identifies the critical technological frontiers needed to scale superconducting quantum computers beyond a handful of qubits into fault-tolerant architectures. It argues for modular QPU designs, scalable cryogenic and cryogenic-electronic infrastructure, and integrated control and software stacks, all supported by standardized testbeds and industry-focused foundry models. Key contributions include a structured set of design considerations across modules, cryogenics, wiring, electronics, control, calibration, error suppression/correction/mitigation, and verification, along with recommendations for ecosystem-building and workforce development. The practical impact is a coordinated, multi-institutional path toward scalable, reliable quantum processors capable of supporting FTQC with manageable cost and maintainability.

Abstract

Experiments with superconducting quantum processors have successfully demonstrated the basic functions needed for quantum computation and evidence of utility, albeit without a sizable array of error-corrected qubits. The realization of the full potential of quantum computing centers on achieving large scale fault-tolerant quantum computers. Science, engineering and industry advances are needed to robustly generate, sustain, and efficiently manipulate an exponentially large computational (Hilbert) space as well as supply the number and quality components needed for such a scaled system. In this article, we suggest critical areas of quantum system and ecosystem development, with respect to the handling and transmission of quantum information within and out of a cryogenic environment, that would accelerate the development of quantum computers based on superconducting circuits.

Paper Structure

This paper contains 25 sections, 4 figures, 1 table.

Table of Contents

  1. Introduction
  2. Modular Quantum Processors
  3. Defining a Module
  4. Engineering/Implementation Considerations
  5. Quantum Error Correction and Modularity
  6. Cryogenic Systems
  7. Optimized Temperatures and Cooling Powers for Cryostat Stages
  8. Power
  9. Rare resource utilization: $^{3}$He volume per qubit
  10. Cryogenic Electronics
  11. Testbeds for Cryogenic Electronics and Components, and Standardization Considerations
  12. Cryogenic Wiring, Integration and Technology Foundries
  13. Control Hardware
  14. Functionality and Reliability
  15. Technology Implementation
  16. ...and 10 more sections

Figures (4)

  • Figure 1: Modular QPU Approaches: (a) Interconnected processing units linked by on-chip microwave transmission lines, (b) separate QPU chips connected by a linker chip, (c) independently packaged QPUs connected by cabling in an single cryostat, and (d) independent QPUs linked by either native microwave frequency links of approximately one or more meters, or via conversion to itinerant optical photons in different cryostats for greater than 1000 cm.
  • Figure 2: Example evolution of fridge extensibility to data center size. A contiguous volume is established through connection of fridge modules. Quantum processing chips are also modular connected using l-couplers as defined in Bravyi et al.bravyi_future_2022. Commercial systems consisting of two dilution units, $\mathcal{O}$(25 $\mu$W) cooling power at the mixing chamber, and two to three pulse tubes has become a commonly used size and is a conceptual starting point for practical fridge module cooling powers, volume, weight, and cost. A third PT or some other source of cooling power would be needed for the elec. cntrl. stage.
  • Figure 3: (a) Functional relationship and (b) conceptual engagement timeline of technology foundries, QC integrators and test services.
  • Figure 4: Summary of major recommendations