An Energy-Efficient Adiabatic Capacitive Neural Network Chip

TL;DR

This work tackles energy-efficient AI at the edge by implementing a mixed-signal adiabatic capacitive neural network (ACNN) in 130 nm CMOS that recycles energy via a Power Clock. The authors demonstrate a two-layer ACNN with 16 single-cycle MAC engines, mapping a TensorFlow-trained 64-input, 12-hidden, 4-output network to on-chip capacitances, achieving >95% accuracy on 8×8 binary images with <2.7% deviation from software. Across five fabricated chips, the approach shows robust cross-chip classification with substantial energy savings: about 2.1×–2.8× at small operation counts and up to 6.8× at higher counts relative to a CMOS baseline, aided by adiabatic energy recovery and a routing layer for scalable multi-layer design. The results indicate practical viability for energy-constrained edge-AI deployment, offering a modular, tileable architecture tolerant to process variation and suitable for scaling toward larger, more complex neuromorphic systems.

Abstract

Recent advances in artificial intelligence, coupled with increasing data bandwidth requirements, in applications such as video processing and high-resolution sensing, have created a growing demand for high computational performance under stringent energy constraints, especially for battery-powered and edge devices. To address this, we present a mixed-signal adiabatic capacitive neural network chip, designed in a 130$nm$ CMOS technology, to demonstrate significant energy savings coupled with high image classification accuracy. Our dual-layer hardware chip, incorporating 16 single-cycle multiply-accumulate engines, can reliably distinguish between 4 classes of 8x8 1-bit images, with classification results over 95\%, within 2.7\% of an equivalent software version. Energy measurements reveal average energy savings between 2.1x and 6.8x, compared to an equivalent CMOS capacitive implementation.

Figures (9)

• Figure 1: a) A standard switched non-adiabatic RC circuit, with a DC supply, where an input signal controls the switch state; b) An adiabatic RC circuit, with an inductive AC supply, where energy is recovered before the switch is grounded, leading to higher energy efficiency; c) Adiabatic and non-adiabatic $V_{C}$ node voltage response over two input signal cycles; d) Current response showing large current surges in the non-adiabatic circuit; e) Net energy response where adiabatic energy recovery and lower currents lead to significantly reduced net energy dissipation.
• Figure 2: The ACN computational workhorse: a) Schematic of a DTSC ACN with a single power clock signal $PC$, an $N$-bit input vector $x$, $N$ synapse capacitors, threshold logic unit and ACN output, $y$; b) Experimentally measured oscilloscope trace of the primary ACN signals illustrating operational timings of one of the 12 1-bit input ACNs in our chip; c) 130$nm$ CMOS layout of the same ACN.
• Figure 3: End-to-end adiabatic image classification: a) 64x12x4 TensorFlow-trained software ANN arrow classifier with 64 1-bit inputs $x$, weights $w$, software bias $\tau$ and Heaviside activation function, $f_{act}$; b) chip architecture block diagram of mapped ACNN implementation; c) contrast-enhanced micro-photograph of the ACNN 130$nm$ chip; d) stacked oscilloscope traces showing ACNN outputs across 4 independent functional test operations using $PC1$ for the ACN layers and a separate $PC2$ for the routing layer. Blue arrows represent data transitions between layers.
• Figure 4: ACNN chip results: a) Cross-chip classification results as box-and-whisker plots showing median, InterQuantile Range (IQR), with whiskers at 1.5IQR. One outlier is shown for Chip3. Hardware results annotated with sample mean; b) Cross-chip $PC1$$E_{SOP}$ median energy results with 1.5IQR error bars. Energy calculated over different numbers of operations, across 4 test images and 5 iterations per test, with jittered grey operation samples to aid visualization; c) Boxplot of dissipated SOP chip energy after several operations, without significant classification errors, using 4 data samples and 5 test iterations per sample. Chip result annotated with median energy and number of operations (ops); d) Comparison of hardware versus ACNN post-layout and CCNN schematic simulations.
• Figure 5: ACNN configuration: a) Capacitance value distribution across all 12 L1 ACNs and 4 $L2$ ACNs, showing contributions from the synapse, bias and ballast capacitors; b) Pie-chart showing contributions to the total ACNN capacitance of 51$pF$. Note, controlling the swing of membrane voltages to be constrained between 100$mV$ and 1.0$V$ is expensive; c) Distribution of synapse capacitance values between 8$fF$ and $80fF$; d) Distribution of quantization errors between all the required mapped 8-bit capacitance values and predicted post-layout capacitance values, with an average error of 0.53$fF$.