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Development of a Central Trigger Processor board for the Advanced SiPM based camera of the CTA Large-Sized Telescopes

A. Pérez-Aguilera, M. Molina-Delicado, T. Dietrich, L. A. Tejedor, J. A. Barrio, A. Upegui, Q. Berthet, J. Buces, D. Nieto, D. Martín-Domínguez, T. Miener

Abstract

We present ongoing work on the Central Trigger Processor board (CTPb), a trigger subsystem for the future advanced SiPM-based Large-Sized Telescope (LST) camera of the Cherenkov Telescope Array Observatory (CTAO). The camera will implement a fully digital trigger, exploiting the increased resolution to improve discrimination of low-energy $γ$-ray events from Night Sky Background noise. This approach aims to enhance telescope sensitivity while satisfying strict timing and data rate constraints. We describe the CTPb conceptual design and report initial results from hardware prototypes under evaluation within this next-generation trigger architecture.

Development of a Central Trigger Processor board for the Advanced SiPM based camera of the CTA Large-Sized Telescopes

Abstract

We present ongoing work on the Central Trigger Processor board (CTPb), a trigger subsystem for the future advanced SiPM-based Large-Sized Telescope (LST) camera of the Cherenkov Telescope Array Observatory (CTAO). The camera will implement a fully digital trigger, exploiting the increased resolution to improve discrimination of low-energy -ray events from Night Sky Background noise. This approach aims to enhance telescope sensitivity while satisfying strict timing and data rate constraints. We describe the CTPb conceptual design and report initial results from hardware prototypes under evaluation within this next-generation trigger architecture.

Paper Structure

This paper contains 5 sections, 4 figures, 1 table.

Table of Contents

  1. Introduction
  2. The Central Trigger Processor board
  3. L2 trigger algorithms
  4. Setup and results
  5. Conclusion

Figures (4)

  • Figure 1: (Left) Pixels distribution in the camera, each colored area represents the corresponding pixels assigned to each FEB. The camera division shows the area corresponding to each processing FPGA at the CTPb. (Right) FPGA disposition at the CTPb and the high-speed connections between them.
  • Figure 2: (Left) Hexagonal convolution over a L1 trigger region, taking into account three time frames. (Right) Four consecutive frames of a simulated 68 GeV $\gamma$-ray event. The first column shows the raw digitized SiPM signals; the second shows the triggered clusters after the L1; the third shows the triggered clusters after the TDSCAN.
  • Figure 3: Photograph showing the manufactured PCB with the cable to complete the data link loop for tests.
  • Figure 4: (Left) Framework used to test a TDSCAN instance. Only the main modules are shown. Secondary modules, such as cross-clock domain synchronizers, are omitted for clarity. (Right) Detail of the TDSCAN implementation, for these tests the values $\epsilon_{xy} = 1$ and $\epsilon_t = 1$ were used, so the frame window is 3 and the convolution kernel is 7 pixels.