ReadyPower: A Reliable, Interpretable, and Handy Architectural Power Model Based on Analytical Framework

TL;DR

The paper tackles inaccuracies of traditional analytical architecture-level power models and the adoption barriers of ML-based approaches. It proposes ReadyPower, an analytical framework that injects architecture-, implementation-, and technology-level parameters into McPAT, with a learning-based method for some parameters and a McPAT-compatible interface. Through experiments on BOOM and XiangShan, ReadyPower achieves superior accuracy (MAPE and correlation) and robustness across training data distributions and cross-technology transfer, outperforming baselines including ML calibrations. The results demonstrate ReadyPower’s reliability, interpretability, and practicality for industry use in early power optimization and design space exploration.

Abstract

Power is a primary objective in modern processor design, requiring accurate yet efficient power modeling techniques. Architecture-level power models are necessary for early power optimization and design space exploration. However, classical analytical architecture-level power models (e.g., McPAT) suffer from significant inaccuracies. Emerging machine learning (ML)-based power models, despite their superior accuracy in research papers, are not widely adopted in the industry. In this work, we point out three inherent limitations of ML-based power models: unreliability, limited interpretability, and difficulty in usage. This work proposes a new analytical power modeling framework named ReadyPower, which is ready-for-use by being reliable, interpretable, and handy. We observe that the root cause of the low accuracy of classical analytical power models is the discrepancies between the real processor implementation and the processor's analytical model. To bridge the discrepancies, we introduce architecture-level, implementation-level, and technology-level parameters into the widely adopted McPAT analytical model to build ReadyPower. The parameters at three different levels are decided in different ways. In our experiment, averaged across different training scenarios, ReadyPower achieves >20% lower mean absolute percentage error (MAPE) and >0.2 higher correlation coefficient R compared with the ML-based baselines, on both BOOM and XiangShan CPU architectures.baselines, on both BOOM and XiangShan CPU architectures.

Figures (8)

• Figure 1: The ReadyPower framework. ReadyPower fixes the discrepancies between real processor implementation and classical power models. It introduces new architecturally interpretable parameters at the architecture, implementation, and technology levels within the analytical framework.
• Figure 2: The methodology overview of ReadyPower.
• Figure 3: Accuracy comparison between our proposed ReadyPower and four baseline methods on BOOM and XiangShan CPUs. Each bar is the average across all training scenarios, including Balance, Small, and Large.
• Figure 4: Prediction visualization on BOOM CPU. It shows that ReadyPower can achieve high accuracy in ALL training scenarios while ML-based methods are inaccurate in Small and Large training scenarios on BOOM.
• Figure 5: Prediction visualization on XiangShan CPU. It shows ReadyPower can achieve high accuracy in ALL training scenarios while ML-based methods are inaccurate in Small and Large scenarios on XiangShan.