VeBPF Many-Core Architecture for Network Functions in FPGA-based SmartNICs and IoT

TL;DR

The paper tackles the bottleneck of network-function acceleration on resource-limited FPGA platforms by introducing VeBPF, a configurable many-core architecture whose Processing Elements execute eBPF bytecode. Each VeBPF core is an eBPF ISA-compliant Verilog CPU with a Harvard memory layout and supports single-clock-cycle rule switching, enabling rapid multi-rule processing across many cores. The architecture features specialized modules for packet slicing, DMA, data loading, multi-rule programming, scheduling, and result analysis, all controlled by a RISC-V m-plane and orchestrated to maximize parallelism while minimizing resource usage. An automatic testing framework and an open-source release accompany the design, and a firewall demonstration on an IoT FPGA shows line-rate packet filtering and significant offloading of the main processor. This work demonstrates that VeBPF can deliver scalable, low-latency network processing on both low-end IoT FPGAs and high-end SmartNICs, with practical implications for network security and acceleration.

Abstract

FPGA-based SmartNICs and IoT devices integrating soft-processors for network function execution have emerged to address the limited hardware reconfigurability of DPUs and MCUs. However, existing FPGA-based solutions lack a highly configurable many-core architecture specialized for network packet processing. This work presents VeBPF many-core architecture, a resource-optimized and highly configurable many-core architecture composed of custom VeBPF (Verilog eBPF) CPU cores designed for FPGA-based packet processing. The VeBPF cores are eBPF ISA compliant and implemented in Verilog HDL for seamless integration with existing FPGA IP blocks and subsystems. The proposed many-core architecture enables parallel execution of multiple eBPF rules across multiple VeBPF cores, achieving low-latency packet processing. The architecture is fully parameterizable, allowing the number of VeBPF cores and eBPF rules to scale according to application requirements and available FPGA resources. eBPF rules can be dynamically updated at run time without requiring FPGA reconfiguration, enabling flexible and adaptive network processing. The design incorporates hardware and computer architecture optimizations that support deployment across a wide range of platforms, from low-end FPGA-based IoT devices to high-end FPGA-based SmartNICs. In addition, we present automated testing and simulation frameworks developed using open-source tools such as Python and Cocotb. The VeBPF cores, many-core architecture, control software libraries, and simulation infrastructure are released as open source to support further research in FPGA-based many-core systems, eBPF acceleration, SmartNICs, IoT, and network security.

Figures (9)

• Figure 1: VeBPF CPU core computer architecture overview.
• Figure 2: Overview of the VeBPF many-core architecture.
• Figure 3: VeBPF Network Packet Slicer and DMA Module
• Figure 4: VeBPF Many-core Data Loader Module
• Figure 5: VeBPF many-core multi-rule program loader module