Bounded Dynamic Level Maintenance for Efficient Logic Optimization

TL;DR

This work tackles the bottleneck of unbounded dynamic level maintenance during iterative, level-constrained logic optimization on DAG-based representations (AIGs). It introduces boundLM, a bounded dynamic algorithm that maintains partial topological order, node levels, and reverse levels with total time $O(|V| \Delta \log \Delta)$ for $|V|$ updates, where $\Delta$ is the largest update size. The approach reduces the affected region during updates and avoids global recomputation, yielding substantial speedups (average 6.4× overall) and dramatic reductions in level maintenance time (up to ~1000×) without sacrificing QoR. Experiments on large-scale benchmarks validate scalability and boundedness, showing strong gains for rewrite, refactor, and resub operations, including zero-gain settings. This work provides a practical paradigm for scalable logic synthesis via dynamic graph algorithms.

Abstract

Logic optimization constitutes a critical phase within the Electronic Design Automation (EDA) flow, essential for achieving desired circuit power, performance, and area (PPA) targets. These logic circuits are typically represented as Directed Acyclic Graphs (DAGs), where the structural depth, quantified by node level, critically correlates with timing performance. Modern optimization strategies frequently employ iterative, local transformation heuristics (\emph{e.g.,} \emph{rewrite}, \emph{refactor}) directly on this DAG structure. As optimization continuously modifies the graph locally, node levels require frequent dynamic updates to guide subsequent decisions. However, a significant gap exists: existing algorithms for incrementally updating node levels are unbounded to small changes. This leads to a total of worst complexity in $O(|V|^2)$ for given local subgraphs $\{ΔG_i\}_{i=1}^{|V|}$ updates on DAG $G(V,E)$. This unbounded nature poses a severe efficiency bottleneck, hindering the scalability of optimization flows, particularly when applied to large circuit designs prevalent today. In this paper, we analyze the dynamic level maintenance problem endemic to iterative logic optimization, framing it through the lens of partial topological order. Building upon the analysis, we present the first bounded algorithm for maintaining level constraints, with $O(|V| Δ\log Δ)$ time for a sequence $|V|$ of updates $\{ΔG_i\}$, where $Δ= \max_i \|ΔG_i\|$ denotes the maximum extended size of $ΔG_i$. Experiments on comprehensive benchmarks show our algorithm enables an average 6.4$\times$ overall speedup relative to \rw and \rf, driven by a 1074.8$\times$ speedup in the level maintenance, all without any quality sacrifice.

Figures (8)

• Figure 1: Motivation example: synthesis flow overview and its runtime breakdown.
• Figure 2: Example of a local optimization on AIG.
• Figure 3: The negligible efficiency gain of lazy level update.
• Figure 4: Example of partial topological order maintenance for replacing $x$ by $x^{\prime}$.
• Figure 5: Example of reverse level $\mathcal{R}$ computation for replacing $6$ by $14$. The $\mathcal{R}$ of each node is annotated below its node.

Theorems & Definitions (18)

• Example 1
• Example 2
• Theorem 1
• Example 3
• Theorem 2
• proof
• Theorem 3
• proof
• Theorem 4
• proof