DreamRAM: A Fine-Grained Configurable Design Space Modeling Tool for Custom 3D Die-Stacked DRAM

TL;DR

DreamRAM addresses the need for systematic exploration of custom 3D die-stacked DRAM by offering a parameterized analytical framework that spans MAT, subarray, bank, and inter-bank levels, including a novel MAT routing scheme (DLOMAT). It models bandwidth, capacity, energy, latency, and area, calibrated to HBM3/HBM2E, and enables large-scale design-space sweeps (up to 2.8M configurations) with fine-grained tunables. The study demonstrates substantial potential gains across workloads, showing designs with significantly higher bandwidth and capacity while reducing energy per bit under iso-criteria, and provides an open-source tool for workload-tailored memory design. These results highlight the practical impact of workload-aware memory customization in next-generation 3D DRAM architectures.

Abstract

3D die-stacked DRAM has emerged as a key technology for delivering high bandwidth and high density for applications such as high-performance computing, graphics, and machine learning. However, different applications place diverse and sometimes diverging demands on power, performance, and area that cannot be universally satisfied with fixed commodity DRAM designs. Die stacking creates the opportunity for a large DRAM design space through 3D integration and expanded total die area. To open and navigate this expansive design space of customized memory architectures that cater to application-specific needs, we introduce DreamRAM, a configurable bandwidth, capacity, energy, latency, and area modeling tool for custom 3D die-stacked DRAM designs. DreamRAM exposes fine-grained design customization parameters at the MAT, subarray, bank, and inter-bank levels, including extensions of partial page and subarray parallelism proposals found in the literature, to open a large previously-unexplored design space. DreamRAM analytically models wire pitch, width, length, capacitance, and scaling parameters to capture the performance tradeoffs of physical layout and routing design choices. Routing awareness enables DreamRAM to model a custom MAT-level routing scheme, Dataline-Over-MAT (DLOMAT), to facilitate better bandwidth tradeoffs. DreamRAM is calibrated and validated against published industry HBM3 and HBM2E designs. Within DreamRAM's rich design space, we identify designs that achieve each of 66% higher bandwidth, 100% higher capacity, and 45% lower power and energy per bit compared to the baseline design, each on an iso-bandwidth, iso-capacity, and iso-power basis.

Figures (7)

• Figure 1: The DreamRAM framework.
• Figure 2: HBM3 organization at the (a) stack, (b) inter-bank, (c) bank/subarray, and (d) MAT levels.
• Figure 3: (a) A conventional MAT. (b) Proposed Dataline-over-MAT (DLOMAT). In both, 1 line represents 4 wires.
• Figure 4: Projection of design space onto energy and bandwidth, colored by tiers. The square is the DreamRAM baseline HBM3.
• Figure 5: Paretos for each tier per application scenario. The left plot depicts the full design space, while the right plot is capacity-filtered per application. As additional parameters become available in each tier, the frontier shifts monotonically toward the ideal.