Characterization of CRYO ASIC for charge readout in the nEXO experiment

TL;DR

The paper addresses the need for a low-noise, in-LXe charge readout solution for the nEXO tonne-scale LXe TPC by presenting the CRYO ASIC, a 64-channel cryogenic System-on-Chip with an integrated pulser and on-chip regulation. It validates performance through cryogenic chamber and LXe stand tests, showing gain stability better than $0.2\%$ over $24$ hours and ENC around $156\,e^{-}$ at a gain of $28.6\,\mathrm{mV/fC}$ and $1.2\,\mu\mathrm{s}$ peaking time, with LXe noise in good agreement with simulations. The study also investigates boiling due to chip heat and demonstrates mitigation by elevating the LXe system pressure toward the nominal $\sim0.15$ MPa, ensuring no degradation of performance. Overall, CRYO ASIC proves to be a viable, low-noise, in-LXe charge readout solution for nEXO and informs future deployment steps with sensor tiles and radiopure cabling.

Abstract

nEXO is a proposed next-generation experiment searching for the neutrinoless double beta decay of $^{136}$Xe using a tonne-scale liquid xenon (LXe) time projection chamber (TPC). To image the ionization signals from events in the liquid xenon, the detector will employ metallized fused-silica charge collection tiles instrumented with cryogenic application-specific integrated circuits (ASICs), referred to as CRYO ASIC, which are designed to operate directly in LXe to minimize input capacitance and pick-up noise. Here we present the performance of the CRYO ASIC mounted on an auxiliary printed circuit board and evaluated both in a cryogenic environmental chamber and in a dedicated LXe test stand. We demonstrate that the ASICs achieve the desired performance at liquid xenon temperatures, showing a gain stability better than 0.2% over 24-hour operation and reliable in-situ calibration using an on-chip pulser. In the LXe test stand, we show that boiling caused by the chip heat dissipation can be mitigated by operating the system above ~0.1 MPa. The in-LXe noise measured agrees with simulation, which indicates it the $150~e^-$ design requirement can be satisfied. These results establish CRYO ASIC as a viable low-noise in-LXe charge readout solution for nEXO.

Figures (11)

• Figure 1: Functional block diagram of the CRYO ASIC and the design specifications of the nEXO-specific implementation.
• Figure 2: Photo of the CRYO ASIC Cold Board system. Left: The CRYO ASIC mounted on a custom PCB (Cold Board) and a zoom view of the ASIC wire bonded to the board below a protective cover. The 64 input channels are loaded with 22 pF or 33 pF capacitors. Right: the cold board communicates with the ePix board and the adapter board for data acquisition.
• Figure 3: The CRYO ASIC FEMB Board is enclosed in an RF shielded box, with the two CRYO ASICS protected beneath acrylic covers. It interfaces with the adapter board and is controlled via the commercial FPGA board.
• Figure 4: A photo of the liquid nitrogen-cooled cryogenic test chamber. The FEMB board is placed in the chamber connected to the DAQ system at room temperature. An external calibration board (purple), plugged into the back of the FEMB board for gain calibration studies, can also be seen in the photo.
• Figure 5: Liquid xenon test stand for CRYO ASIC testing. Left: Photo of the inner LXe chamber installed in the outer cryostat. Right: schematic drawing of the inner LXe chamber and placement of the cold board inside the chamber.