L2 Ethernet Switch VLSI Implementation

TL;DR

This work presents an open-source L2 Ethernet switch design implementing GMII-based ingress and egress paths, MAC learning, and a centralized memory with VOQs to achieve high throughput and low latency. It details RTL-level modules including RX/TX paths, SRAM, free list, crossbar, address learn table, router, and arbiters, and analyzes design tradeoffs via a complete RTL-to-GDSII flow and timing/power results. Key contributions include a stack-based free list with reference counters for flood safety, a pseudo-LRU eviction for a compact address table, and a thorough discussion of memory bottlenecks and potential optimizations. The findings underscore the feasibility of open-source L2 switch implementations and outline concrete paths for performance, area, and reliability improvements in future work.

Abstract

Ethernet switches are foundational to the global internet infrastructure. These devices route packets of data on a local area network between source addresses to destination media access control addresses. On the L2 layer of the Open Systems Interconnections model, Ethernet switches take in digitized data from a Media Independent Interface and send it to the corresponding output port for the destination address. Switches need to handle parallel input and output streams from each port, prioritizing throughput, efficiency, and packet integrity. Due to the confidential nature of the networking device industry, there do not exist many open source implementations of switching fabrics. We propose an open source design for an L2 Ethernet switch along with the power, performance, and area tradeoffs for architecture decisions.

Figures (21)

• Figure 1: Ethernet Frame Diagram ethernet_frame
• Figure 2: Overall Top Architecture Diagram
• Figure 3: Top level schematic
• Figure 4: RX Parsing and Sending Packet to Memory
• Figure 5: Packet drop functionality with corrupted CRC