Neuromorphic Processor Employing FPGA Technology with Universal Interconnections

TL;DR

The paper tackles the shortage of accessible neuromorphic hardware by delivering a low-cost, open-source FPGA-based processor on a Zynq-7000 that supports all-to-all SNN connectivity and a configurable leaky integrate-and-fire model, reconfigurable in real time via UART. It details the hardware design, including a modular UART-driven interface, a register bank, and a core SNN with scalable connectivity, and validates the approach on Iris and MNIST benchmarks with low power consumption. The main contributions are the open, adaptable hardware platform, the two benchmark demonstrations, and the demonstration of runtime configurability without FPGA re-synthesis. This work provides a practical, research-grade tool for rapid prototyping and education in neuromorphic computing, enabling energy-efficient, real-time spike-based inference on commodity FPGA hardware.

Abstract

Neuromorphic computing, inspired by biological neural systems, holds immense promise for ultra-low-power and real-time inference applications. However, limited access to flexible, open-source platforms continues to hinder widespread adoption and experimentation. In this paper, we present a low-cost neuromorphic processor implemented on a Xilinx Zynq-7000 FPGA platform. The processor supports all-to-all configurable connectivity and employs the leaky integrate-and-fire (LIF) neuron model with customizable parameters such as threshold, synaptic weights, and refractory period. Communication with the host system is handled via a UART interface, enabling runtime reconfiguration without hardware resynthesis. The architecture was validated using benchmark datasets including the Iris classification and MNIST digit recognition tasks. Post-synthesis results highlight the design's energy efficiency and scalability, establishing its viability as a research-grade neuromorphic platform that is both accessible and adaptable for real-world spiking neural network applications. This implementation will be released as open source following project completion.

Figures (8)

• Figure 1: Processor Architecture
• Figure 2: Architecture for All-to-All Neuron Connectivity with Selective Routing
• Figure 3: Block Diagram of Parametric SNN Neuron Network
• Figure 4: Iris dataset architecture
• Figure 5: Simulation Waveform Analysis for Iris Dataset