Eight-Qubit Operation of a 300 mm SiMOS Foundry-Fabricated Device

TL;DR

This work addresses the challenge of scaling silicon spin qubits in CMOS to medium-sized arrays by demonstrating an eight-qubit linear quantum-dot device fabricated in a 300 mm CMOS-compatible process. The authors combine four double quantum-dot unit cells with cascaded readout, ESR-based single-qubit control, and exchange-based two-qubit gates to achieve coherent operation beyond two qubits. They report coherence times up to $T_2^* = 41(2)~\mu s$ and $T_2^{\mathrm{Hahn}} = 1.31(4)~\mathrm{ms}$, along with Rabi frequencies of 141–204.5 kHz, individual qubit addressability via a g-factor spread of $\Delta g = 2.17\times 10^{-3}$, and successful demonstration of a neighboring two-qubit exchange gate. The results validate the viability of scaling silicon spin qubits within industrial CMOS platforms, marking a step toward scalable, fault-tolerant quantum processors with integrated control and readout.

Abstract

Silicon spin qubits are a promising candidate for quantum computing, thanks to their high coherence, high controllability and manufacturability. However, the most scalable complementary metal-oxide-semiconductor (CMOS) based implementations have so far been limited to a few qubits. Here, to take a step towards large scale systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in 300 mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double dot pairs, exhibiting Ramsey dephasing times $T_2^*$ up to 41(2) $μ$s and Hahn-echo coherence times $T_2^{\mathrm{Hahn}}$ up to 1.31(4) ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling simultaneous high-fidelity measurements of the entire multi-qubit array. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We demonstrate here that we can scale silicon spin qubit arrays to medium-sized arrays of 8 qubits while maintaining coherence of the system.

Figures (10)

• Figure 1: Overview of operation and calibration of 8 dot device.a) Schematic of cross section of the device depicting silicon ($^{28}$Si) substrate, oxide layers (shades of gray), and plunger electrodes (P$_i$ and SET$_i$) and barrier (J$_i$ and B$_i$) gates. The electric potential is visualized within the Si substrate with the used electron occupancy. b) Spin-to-charge conversion readout techniques of the lateral DQDs: i) P1-P2 and P7-P8 via direct SET readout and the central DQDs; ii) P3-P4 and P5-P6 via cascaded readout facilitated by electrons in lateral dots. The left side exemplifies charge movement for odd spin states (green arrows), while the right side exemplifies Pauli spin blockade for even spin states (red arrows). c) Charge stability maps in isolated mode for i) P1--P2, ii) P3--P4, iii) P5--P6, and iv) P7--P8. Red circles mark the charge configuration used for the measured qubits d) Rabi-chevron measurements for qubits 1-8, shown in i)-viii) respectively.
• Figure 2: Qubit characteristics summary.a) Larmor frequencies, b) Rabi frequencies, c) Ramsey coherence times $T_2^*$, d) Hahn echo coherence times $T_2^{\rm Hahn}$. The box symbol shows the spread of values as well as their mean and standard deviation.
• Figure 3: Two qubit exchange in P1-P2.a) Exchange decoupled 'fingerprint' map at a fixed exchange period of 1µ s for barrier gate voltage J1 vs P1-P2 detuning voltage. b) Exchange oscillations vs barrier gate voltage J1. The scan is performed along the white dotted line in a). c) Phase calibration of controlled-phase gate (CZ). d) Line cuts along black and orange line in c).
• Figure 4: Electron loading sequence of the entire device.a) Initial DC operating potential. b) Flooding the device from both sides with a 2-dimensional electron gas from the SET islands symmetric around J4. c) Set calibrated loading voltages (P4, P5) and barrier voltages (J4, J5) to reduce the Fermi sea to the desired integer of electrons. d) Electrons are trapped to central dots by applying blocking potentials (J2, P3, J3 and J5, P6, J6). e) Similar to (c) but in lateral dots, loading voltages (P2 and P7) and barrier voltages (J1 and J7). f) Similar to (d) blocking potentials to trap electrons under P2 and P7 while pushing out the Fermi sea. g) Returning to the initial DC operating potential.
• Figure 5: Isolated mode stability maps of P7P8 DQD | Electrons are incrementally loaded into the double dot using the technique shown in Extended Figure \ref{['supp:loading_sequence']}. The higher the voltage of P7 during the sequence stop shown in Extended Figure \ref{['supp:loading_sequence']}e, the more electrons will be captured in P7--P8. The loading voltage decreases with an increased number of electrons per DQD leon_coherent_2020. Inter-dot transitions (vertical) are extending, following charge occupancy numbers, thus tunnel coupling among DQDs before forming a quantum dot under the intermediate J-gate is enhanced as more electrons are accumulated. The red line in the four electron maps indicates the scan shown in Extended Figure \ref{['supp:ex_turonon']}a.