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A Vertically Integrated Framework for Templatized Chip Design

Jeongeun Kim, Christopher Torng

TL;DR

Marionette addresses the challenge of software developers prototyping custom hardware by translating object-oriented software into a vertically integrated hardware stack that preserves object structure and protocols via session-type specifications. It introduces a formal equivalence verification framework that ensures software-level interactions are realized identically in RTL and in layout, coupled with interconnect designs (snoopy bus vs crossbar) and a template-based, correctness-by-construction layout library. Key contributions include cross-layer session-type equivalence checking, data-aware verification, scalable implementation, and a templated optimization flow that makes hardware design more accessible to software-first users. Evaluation on CNN modules demonstrates that a snoopy-bus network can outperform Arduino-based prototyping for MAC-heavy workloads, validating the practicality of software-driven chip prototyping while highlighting trade-offs in area, latency, and power.

Abstract

Developers who primarily engage with software often struggle to incorporate custom hardware into their applications, even though specialized silicon can provide substantial benefits to machine learning and AI, as well as to the application domains that they enable. This work investigates how a chip can be generated from a high-level object-oriented software specification, targeting introductory-level chip design learners with only very light performance requirements, while maintaining mental continuity between the chip layout and the software source program. In our approach, each software object is represented as a corresponding region on the die, producing a one-to-one structural mapping that preserves these familiar abstractions throughout the design flow. To support this mapping, we employ a modular construction strategy in which vertically composed IP blocks implement the behavioral protocols expressed in software. A direct syntactic translation, however, cannot meet hardware-level efficiency or communication constraints. For this reason, we leverage formal type systems based on sequences that check whether interactions between hardware modules adhere to the communication patterns described in the software model. We further examine hardware interconnect strategies for composing many such modules and develop layout techniques suited to this object-aligned design style. Together, these contributions preserve mental continuity from software to chip design for new learners and enables practical layout generation, ultimately reducing the expertise required for software developers to participate in chip creation.

A Vertically Integrated Framework for Templatized Chip Design

TL;DR

Marionette addresses the challenge of software developers prototyping custom hardware by translating object-oriented software into a vertically integrated hardware stack that preserves object structure and protocols via session-type specifications. It introduces a formal equivalence verification framework that ensures software-level interactions are realized identically in RTL and in layout, coupled with interconnect designs (snoopy bus vs crossbar) and a template-based, correctness-by-construction layout library. Key contributions include cross-layer session-type equivalence checking, data-aware verification, scalable implementation, and a templated optimization flow that makes hardware design more accessible to software-first users. Evaluation on CNN modules demonstrates that a snoopy-bus network can outperform Arduino-based prototyping for MAC-heavy workloads, validating the practicality of software-driven chip prototyping while highlighting trade-offs in area, latency, and power.

Abstract

Developers who primarily engage with software often struggle to incorporate custom hardware into their applications, even though specialized silicon can provide substantial benefits to machine learning and AI, as well as to the application domains that they enable. This work investigates how a chip can be generated from a high-level object-oriented software specification, targeting introductory-level chip design learners with only very light performance requirements, while maintaining mental continuity between the chip layout and the software source program. In our approach, each software object is represented as a corresponding region on the die, producing a one-to-one structural mapping that preserves these familiar abstractions throughout the design flow. To support this mapping, we employ a modular construction strategy in which vertically composed IP blocks implement the behavioral protocols expressed in software. A direct syntactic translation, however, cannot meet hardware-level efficiency or communication constraints. For this reason, we leverage formal type systems based on sequences that check whether interactions between hardware modules adhere to the communication patterns described in the software model. We further examine hardware interconnect strategies for composing many such modules and develop layout techniques suited to this object-aligned design style. Together, these contributions preserve mental continuity from software to chip design for new learners and enables practical layout generation, ultimately reducing the expertise required for software developers to participate in chip creation.

Paper Structure

This paper contains 22 sections, 5 equations, 15 figures, 3 tables.

Table of Contents

  1. Introduction
  2. System Goals
  3. Marionette Framework
  4. Equivalence Verification Framework Overview
  5. Limitations of the Session Type Approach
  6. Valid Input
  7. Invalid Input
  8. High-Level Abstraction Mapping
  9. Equivalence Checking via Session Type Subtyping
  10. Data-aware Equivalence Verification
  11. Scalable Implementation of Behavioral Equivalence Verification
  12. Network Architecture: Bridging Software Constructs and Physical Hardware
  13. Design Optimization Under Constraints
  14. Goals
  15. Correctness by Construction
  16. ...and 7 more sections

Figures (15)

  • Figure 1: System architecture mapping: the object-oriented structure of the software design is directly reflected in the chip layout.
  • Figure 2: A vertically stacked IP library, integrating software, RTL, and physical design as a single unit, differs from traditional horizontally layered IPs.
  • Figure 3: High-level equivalence verification flow: starting from a vertical IP, only connections between modules that pass inter-layer communication protocol equivalence checks are realized in the chip layout.
  • Figure 4: Example of user software input and the corresponding session type sequence.
  • Figure 5: Valid software input example: program entry point with fixed-size input and valid method calls.
  • ...and 10 more figures

Theorems & Definitions (1)

  • Definition 1: Session Type Equivalence