Graph-Based Bayesian Optimization for Quantum Circuit Architecture Search with Uncertainty Calibrated Surrogates

TL;DR

This work tackles automated design of variational quantum circuits by embedding a graph-based Bayesian optimization loop that uses a structure-aware GIN surrogate with MC dropout to predict performance and uncertainty. By representing circuits as DAGs and incorporating hardware costs and decoherence proxies into a tempered acquisition function, the method efficiently discovers compact, entangling architectures that remain robust under realistic noise. Compared with baselines, the approach achieves faster convergence, better ranking fidelity, and favorable accuracy-cost Pareto frontiers on a cybersecurity dataset, while providing reproducible experimental protocols. The framework demonstrates practicality for near-term quantum machine learning, offering a scalable route to architecture search that respects compilation, routing, and decoherence in hardware-aware optimization.

Abstract

Quantum circuit design is a key bottleneck for practical quantum machine learning on complex, real-world data. We present an automated framework that discovers and refines variational quantum circuits (VQCs) using graph-based Bayesian optimization with a graph neural network (GNN) surrogate. Circuits are represented as graphs and mutated and selected via an expected improvement acquisition function informed by surrogate uncertainty with Monte Carlo dropout. Candidate circuits are evaluated with a hybrid quantum-classical variational classifier on the next generation firewall telemetry and network internet of things (NF-ToN-IoT-V2) cybersecurity dataset, after feature selection and scaling for quantum embedding. We benchmark our pipeline against an MLP-based surrogate, random search, and greedy GNN selection. The GNN-guided optimizer consistently finds circuits with lower complexity and competitive or superior classification accuracy compared to all baselines. Robustness is assessed via a noise study across standard quantum noise channels, including amplitude damping, phase damping, thermal relaxation, depolarizing, and readout bit flip noise. The implementation is fully reproducible, with time benchmarking and export of best found circuits, providing a scalable and interpretable route to automated quantum circuit discovery.

Figures (13)

• Figure 1: Comparison of two quantum circuits with their feature vectors and graph representations. While aggregate scalar features (e.g., gate counts, depth) can appear similar, the graph encoding preserves topological and dependency information critical for distinguishing circuit function. This motivates the use of graph neural networks (GNNs) as structure-aware surrogates in quantum circuit optimization.
• Figure 2: Overview of the hardware-aware, graph-based BO pipeline for VQC circuit search. The workflow proceeds from inputs to results as follows. Data Preparation and Feature Engineering handles preprocessing (§\ref{['ss1']}), after which Circuit Generation specifies the ansatz and mutation operators (§\ref{['ss3']}). Candidates are then represented via Graph Encoding & Surrogates together with QC Feature Extraction, using a GIN with MC-dropout and a feature MLP (§\ref{['ss4']}). Cost Modeling integrates base and mapped hardware costs into the acquisition criterion (§\ref{['ss4']}), while Noise Modeling & Robustness Sweeps configure device-level noise and related analyses (§\ref{['ss2']}). Within BO, we apply cost-aware expected improvement, select the top-$k$ candidates, perform VQC Evaluation, and update and retrain the surrogate (§\ref{['ss5']}). Baselines & Reporting summarize results and comparisons, including accuracy, wall-time, ranking, Pareto and robustness analyses, and final circuit graphs (§\ref{['ss6']}).
• Figure 3: Graph encoding of a quantum circuit. Each node represents a gate instance with one-hot features for gate type, position, and qubit involvement; edges capture temporal and shared-qubit dependencies. The resulting directed graph enables the GIN surrogate to capture structure-dependent circuit behavior.
• Figure 4: Best-found $5$-qubit architecture returned by BO+VQC+GNN. The circuit exhibits alternating single-qubit rotations (e.g., $R_X$, $R_Y$, $R_Z$, $H$) and selective two-qubit entanglers (e.g., $\mathrm{RZZ}$/$\mathrm{CZ}$/$\mathrm{CX}$ depending on the discovered pattern), forming a shallow, cost-efficient design. Reported costs: total gates = [108], CZ gates = [34], depth = [53]. This matches the frontier region where accuracy gains persist while additional two-qubit count yields diminishing returns.
• Figure 5: Wall-time comparison of BO loops. Total BO loop time for BO+VQC+GNN versus BO+VQC+MLP across 8, 10, and 12 qubits, showing comparable efficiency despite richer graph computations due to batched surrogate inference.