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LLMs for Analog Circuit Design Continuum (ACDC)

Yasaman Esfandiari, Jocelyn Rego, Austin Meyer, Jonathan Gallagher, Mia Levy

TL;DR

This work investigates the use of large language models to automate analog circuit layout from netlists under realistic design constraints like DRC and LVS. It progresses from simple masking tasks to sequential placement with Mistral-7B and to all-at-once layout generation with GPT-oss-20B, examining how data representations and prompts influence reliability and generalization. Key findings show that larger, task-specific models can produce non-overlapping, compact layouts that respect symmetry in synthetic data, but real-world nets reveal remaining gaps and parsing challenges that limit deployment. The paper highlights practical directions, including richer structural representations and robust parsing, to advance AI-assisted, constraint-aware analog layout synthesis toward deployable solutions.

Abstract

Large Language Models (LLMs) and transformer architectures have shown impressive reasoning and generation capabilities across diverse natural language tasks. However, their reliability and robustness in real-world engineering domains remain largely unexplored, limiting their practical utility in human-centric workflows. In this work, we investigate the applicability and consistency of LLMs for analog circuit design -- a task requiring domain-specific reasoning, adherence to physical constraints, and structured representations -- focusing on AI-assisted design where humans remain in the loop. We study how different data representations influence model behavior and compare smaller models (e.g., T5, GPT-2) with larger foundation models (e.g., Mistral-7B, GPT-oss-20B) under varying training conditions. Our results highlight key reliability challenges, including sensitivity to data format, instability in generated designs, and limited generalization to unseen circuit configurations. These findings provide early evidence on the limits and potential of LLMs as tools to enhance human capabilities in complex engineering tasks, offering insights into designing reliable, deployable foundation models for structured, real-world applications.

LLMs for Analog Circuit Design Continuum (ACDC)

TL;DR

This work investigates the use of large language models to automate analog circuit layout from netlists under realistic design constraints like DRC and LVS. It progresses from simple masking tasks to sequential placement with Mistral-7B and to all-at-once layout generation with GPT-oss-20B, examining how data representations and prompts influence reliability and generalization. Key findings show that larger, task-specific models can produce non-overlapping, compact layouts that respect symmetry in synthetic data, but real-world nets reveal remaining gaps and parsing challenges that limit deployment. The paper highlights practical directions, including richer structural representations and robust parsing, to advance AI-assisted, constraint-aware analog layout synthesis toward deployable solutions.

Abstract

Large Language Models (LLMs) and transformer architectures have shown impressive reasoning and generation capabilities across diverse natural language tasks. However, their reliability and robustness in real-world engineering domains remain largely unexplored, limiting their practical utility in human-centric workflows. In this work, we investigate the applicability and consistency of LLMs for analog circuit design -- a task requiring domain-specific reasoning, adherence to physical constraints, and structured representations -- focusing on AI-assisted design where humans remain in the loop. We study how different data representations influence model behavior and compare smaller models (e.g., T5, GPT-2) with larger foundation models (e.g., Mistral-7B, GPT-oss-20B) under varying training conditions. Our results highlight key reliability challenges, including sensitivity to data format, instability in generated designs, and limited generalization to unseen circuit configurations. These findings provide early evidence on the limits and potential of LLMs as tools to enhance human capabilities in complex engineering tasks, offering insights into designing reliable, deployable foundation models for structured, real-world applications.

Paper Structure

This paper contains 22 sections, 18 figures, 2 tables.

Table of Contents

  1. Problem Statement
  2. Literature Review
  3. Methodology and Results
  4. Masking
  5. Toy Problem
  6. Netlist Subgroup Masking
  7. Masking for Layout Generation:
  8. Sequential Placement $Seq2Seq$ Layout Design:
  9. Fine-tuning Mistral7B with Synthetic Data v1:
  10. Fine-tuning Mistral7B with Synthetic Data v2:
  11. Mistral7B Evaluation on Real-world Circuits:
  12. Joint $All-at-Once$ Placement Layout Design:
  13. Fine-tuning GPT20B with Synthetic Data v3:
  14. Parsing the LLM Output:
  15. Finetuned GPT-oss-20B Model Evaluation on Real-world Circuits:
  16. ...and 7 more sections

Figures (18)

  • Figure 1: Sample training data for the toy problem with GPT2: masking a number in a grid and having the transformer predict the value of the 4th item in the row preceding the masked row.
  • Figure 2: Sample training data for the 1-D version of the toy problem with GPT2: predicting the index N before the mask, N is 7 in this example.
  • Figure 3: Sample training data for the randomly masked token experiments: 10-integer long sequences with integers between 0-9 with a random number of randomly masked values.
  • Figure 4: An example and illustration of a synthetic netlist group (g0) consisting of 3 subgroups (s0, s1, s2). Each component is defined after an initial [next] token by its terminal connections and group/subgroup membership.
  • Figure 5: Sample training data for the masking for layout generation experiment: one transistor is masked and the model is trained to output the masked transistor
  • ...and 13 more figures