Device/circuit simulations of silicon spin qubits based on a gate-all-around transistor

TL;DR

This work proposes a CMOS-compatible readout scheme for silicon spin qubits using gate-all-around (GAA) transistors, where qubit-state–dependent charge distributions modulate the GAA channel current. It integrates 3D TCAD simulations to capture state-dependent I–V characteristics and SPICE circuit simulations (with Verilog-A) to test an SRAM-based readout that amplifies weak signals at cryogenic temperatures. The study demonstrates that qubit states $|0\rangle_L$ and $|1\rangle_L$ produce distinct current signatures and that a carefully designed readout circuit can discriminate these states with minimized backaction. These results point to a path for dense, CMOS-integrated spin-qubit architectures, while highlighting fabrication and coherence challenges that require further analysis, including density-matrix treatment of measurement backaction. The work advances practical integration of spin qubits into conventional CMOS technology and motivates further exploration of 2D qubit arrays and Type-B configurations.

Abstract

We theoretically investigated the readout process of a spin--qubit structure based on a gate-all-around (GAA) transistor. Our study focuses on a logical qubit composed of two physical qubits. Different spin configurations result in different charge distributions, which subsequently influence the electrostatic effects on the GAA transistor. Consequently, the current flowing through the GAA transistor depends on the qubit's state. We calculated the current-voltage characteristics of the three-dimensional configurations of the qubit and GAA structures, using technology computer-aided design (TCAD) simulations. Moreover, we performed circuit simulations using the Simulation Program with Integrated Circuit Emphasis (SPICE) to investigate whether a readout circuit made from complementary metal--oxide semiconductor (CMOS) transistors can amplify the weak signals generated by the qubits. Our findings indicate that, by dynamically controlling the applied voltage within a properly designed circuit, the readout can be detected effectively based on a conventional sense amplifier.

Figures (13)

• Figure 1: A logical qubit is defined using two coupled quantum dots that incorporate electric spins. In the readout mode, as shown in the figures on the right of (a) and (b), a gate bias $V_{\rm cg}$ is applied to the quantum dots (here, upper quantum dot). The electrons accumulate in the upper quantum dot only when the logical qubit is in the $|1\rangle_L$ state owing to the Pauli exclusion principle.
• Figure 2: (a) A unit of the qubit (two quantum dots) and the GAA transistor. The qubits made of two quantum dots (Fig. 1) are interconnected through GAA transistors. One of the double quantum dots is tunnel-coupled to the transistor channel, while the other is capacitively coupled to the GAA transistors. (b) A qubit-transistor array with the structure shown in Fig.(a).
• Figure 3: An example of stacking the qubit arrays of Fig. \ref{['fig2']}. We call this structure "type-A". (a) A single unit. (b) 2D qubit array of (a). In this case, the GAA structure (green) is surrounded by two qubits (yellow) on two sides ((a)). In the appendix \ref{['sec:Appendix_A']}, a different configuration (type-B) is discussed. The qubits and GAA transistor are surrounded by the common gate via SiO${}_2$, which is not shown in the figure.
• Figure 4: Current-voltage characteristics of the type-A configuration in the initialization step to confirm whether two electrons exist in two coupled quantum dots. (a) $I_D$-$V_D$ and (b) $I_D$-$V_G$ characteristics for the 2.5 nm quantum dot qubit. (c) Three charge distributions in (a) and (b).
• Figure 5: Current-voltage characteristics of the type-A configuration. See Table 1 for the parameters. (a) $I_D$-$V_D$ and (b) $I_D$-$V_G$ characteristics for the 2.5 nm quantum dot qubit. (c) $I_D$-$V_D$ and (d) $I_D$-$V_G$ characteristics for the 5 nm quantum dot qubit. (e) $I_D$-$V_D$ and (f) $I_D$-$V_G$ characteristics for the 10 nm quantum dot qubit.