Moire-Engineered Ferroelectric Transistors for Nearly Trap-free, Low-Power and Non-Volatile 2D Electronics

Abstract

Long-range moire patterns in twisted WSe2 enable a built-in, moire-length-scale ferroelectric polarization that can be directly harnessed in electronic devices. Such a built-in ferroic landscape offers a compelling means to enable ultralow-voltage and non-volatile electronic functionality in two-dimensional materials; however, achieving stable polarization control without charge trapping has remained a persistent challenge. Here, we demonstrate a moire-engineered ferroelectric field-effect transistor (FeFET) utilizing twisted WSe2 bilayers that leverages atomically clean van der Waals interfaces to achieve efficient polarization-channel coupling and trap-suppressed, ultralow-voltage operation (subthreshold swing of 64 mV per decade). The device exhibits a stable non-volatile memory window of 0.10 V and high mobility, exceeding the performance of previously reported two-dimensional FeFET and matching that of advanced silicon-based devices. In addition, capacitance-voltage spectroscopy, corroborated by self-consistent Landau-Ginzburg-Devonshire modeling, indicates ultrafast ferroelectric switching (~0.5 microseconds). These results establish moire-engineered ferroelectricity as a practical and scalable route toward ultraclean, low-power, and non-volatile 2D electronics, bridging atomistic lattice engineering with functional device architectures for next-generation memory and logic technologies.

Figures (6)

• Figure 1: Moiré ferroelectricity and device characteristics (a) Optical micrograph of a representative MoS$_2$/hBN/twisted-WSe$_2$/graphite device. (b) Illustration of ferroelectric domains in twisted WSe$_2$. Green and blue colors represent up and down polarization, respectively. (c)Transfer characteristics ($I_{D}$–$V_{G}$) show a narrow clockwise hysteresis window ($\Delta V_{\mathrm{th}} \approx 0.10~\mathrm{V}$), while the control MoS$_2$/hBN/graphite device exhibits negligible hysteresis, excluding interface traps as the dominant mechanism (c, inset). (d) A schematic of the FeFET stack and the equivalent capacitance model is shown. (e) The calculated polarization–electric field ($P$–$E$) loop using the Landau–Khalatnikov formalism matches the extracted remanent polarization ($P_{r} \approx 0.42~\mu \mathrm{C\,cm^{-2}}$) and coercive field ($E_{c} \approx 0.09~\mathrm{V\,nm^{-1}}$), while the corresponding Landau free-energy profile (f) illustrates the characteristic double-well potential, confirming robust ferroelectric switching in twisted WSe$_2$.
• Figure 2: Drain-bias dependence of subthreshold characteristics in 2D FETs. (a–c) Transfer curves at increasing $V_{\mathrm{DS}}$ ($L_{\mathrm{ch}} = 1~\mu$m) showing stable hysteresis and progressive improvement in subthreshold swing (SS). (d) Point-by-point SS versus drain current ($I_{\mathrm{DS}}$), demonstrating approach to the near-ideal 60 mV dec$^{-1}$ limit across a broad $I_{\mathrm{DS}}$ range. (e) Comparison with a MoS$_2$/hBN control device, highlighting the superior SS ($\sim$64 mV dec$^{-1}$) in the FeFET versus $>$130 mV dec$^{-1}$ in the control.
• Figure 3: Sweep-rate dependence of hysteresis dynamics. (a) Transfer curves ($I_{\mathrm{D}}$–$V_{\mathrm{G}}$) measured at different sweep rates, shifted by 1 V for clarity, showing systematic reduction of hysteresis with increasing rate. (b) Extracted hysteresis width versus sweep rate, fitted using a domain-wall-limited switching model.
• Figure 4: CV spectroscopy of 2D FeFETs. (a) CV characteristics of the MoS$_2$/hBN/twisted-WSe$_2$ FeFET compared with a control device, showing enhanced capacitance (inset: device schematic). (b) Differential $dC/dV_{\mathrm{G}}$ plot displaying a sharp peak for the twisted-WSe$_2$ device, indicative of ferroelectric switching, whereas the control shows a broad peak corresponding to deep depletion or trap response; Lorentzian fits are used to extract the FWHM. (c) Frequency-dependent CV curves of another FeFET reveal an additional ferroelectric switching regime beyond the conventional CV response. (d) $dC/dV_{\mathrm{G}}$ as a function of frequency showing kinetic limitation in domain wall motion. (e) Experimental $C_{\text{total}}$ as a function of frequency at different $V_{\text{BG}}$ values. (f) Extracted $\tau_{\text{it}}$ and $C_{Q}$ as a function of $V_{\text{G}}$. (g) Experimental and simulated two-dimensional CV spectroscopy maps, highlighting the agreement between measurement and self-consistent modeling.
• Figure 5: Simplified equivalent circuits to model MoS$_2$-FeFET C–V. (a) Full equivalent circuit illustrating the formation of the total measured capacitance $C_{\mathrm{para}}$. (b) Schematic of the capacitance measurement configuration, where both the source and drain electrodes are connected to the low terminal, and the top gate is connected to the high terminal. (c) Experimental and simulated total capacitance--voltage ($C_{\mathrm{total}}$--$V_{\mathrm{TG}}$) characteristics of the MoS$_2$ FeFET, showing good agreement in the accumulation regime. (d) Experimental and simulated two-dimensional $C$--$V$ spectroscopy maps, highlighting the consistency between measurement and self-consistent modeling.