Artificial Intelligence-Driven Network-on-Chip Design Space Exploration: Neural Network Architectures for Design

TL;DR

The paper tackles the inverse NoC design problem by reframing it as reverse parameter prediction from target latency and throughput. It introduces a Python-based automated BookSim framework to generate and evaluate a large design space and compares three neural architectures—MLP, CVAE, and a conditional diffusion model—for reverse design. The diffusion model achieves the best predictive accuracy on unseen data and, via BookSim-based validation, offers the most reliable balance between diversity and fidelity, enabling rapid NoC co-design. The work demonstrates substantial speedups in exploration time and highlights the potential and limitations of generative approaches for hardware design optimization.

Abstract

Network-on-Chip (NoC) design requires exploring a high-dimensional configuration space to satisfy stringent throughput requirements and latency constraints. Traditional design space exploration techniques are often slow and struggle to handle complex, non-linear parameter interactions. This work presents a machine learning-driven framework that automates NoC design space exploration using BookSim simulations and reverse neural network models. Specifically, we compare three architectures - a Multi-Layer Perceptron (MLP),a Conditional Diffusion Model, and a Conditional Variational Autoencoder (CVAE) to predict optimal NoC parameters given target performance metrics. Our pipeline generates over 150,000 simulation data points across varied mesh topologies. The Conditional Diffusion Model achieved the highest predictive accuracy, attaining a mean squared error (MSE) of 0.463 on unseen data. Furthermore, the proposed framework reduces design exploration time by several orders of magnitude, making it a practical solution for rapid and scalable NoC co-design.

Figures (5)

• Figure 1: Data preparation workflow: BookSim simulation outputs are cleaned, scaled, and split for supervised training
• Figure 2: MLP architecture for reverse NoC parameter prediction. The network maps 2D performance inputs to 4D configuration outputs.
• Figure 3: Architecture of Conditional Variational Autoencoder (CVAE) with encoder-decoder design.
• Figure 4: Conditional diffusion model: a denoising neural network learns to reverse noisy parameter vectors conditioned on performance metrics.
• Figure 5: End-to-end training and inference flow of the conditional diffusion model with noise schedule and iterative denoising.