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LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout

M. A. Farooq, G. Di Guglielmo, A. Rajagopala, N. Tran, V. A. Chhabria, A. Arora

TL;DR

LUNA tackles the bottleneck of scalable qubit readout by merging a low-cost integrator-based preprocessing stage with LUT-mapped LogicNets, enabling ultra-low-latency, DSP-free FPGA implementations. The approach uses a differential evolution–driven design-space exploration to jointly optimize preprocessing and neural topology, achieving up to ~11x LUT reductions and substantial latency improvements while maintaining state-of-the-art fidelity. Through automated RTL generation and FPGA synthesis, LUNA demonstrates robust performance on standard superconducting readout data, supporting scalable quantum processors and QEC loops. The work highlights a practical path to compact, fast, and reliable qubit readout accelerators that can coexist with large-scale quantum control infrastructures.

Abstract

Qubit readout is a critical operation in quantum computing systems, which maps the analog response of qubits into discrete classical states. Deep neural networks (DNNs) have recently emerged as a promising solution to improve readout accuracy . Prior hardware implementations of DNN-based readout are resource-intensive and suffer from high inference latency, limiting their practical use in low-latency decoding and quantum error correction (QEC) loops. This paper proposes LUNA, a fast and efficient superconducting qubit readout accelerator that combines low-cost integrator-based preprocessing with Look-Up Table (LUT) based neural networks for classification. The architecture uses simple integrators for dimensionality reduction with minimal hardware overhead, and employs LogicNets (DNNs synthesized into LUT logic) to drastically reduce resource usage while enabling ultra-low-latency inference. We integrate this with a differential evolution based exploration and optimization framework to identify high-quality design points. Our results show up to a 10.95x reduction in area and 30% lower latency with little to no loss in fidelity compared to the state-of-the-art. LUNA enables scalable, low-footprint, and high-speed qubit readout, supporting the development of larger and more reliable quantum computing systems.

LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout

TL;DR

LUNA tackles the bottleneck of scalable qubit readout by merging a low-cost integrator-based preprocessing stage with LUT-mapped LogicNets, enabling ultra-low-latency, DSP-free FPGA implementations. The approach uses a differential evolution–driven design-space exploration to jointly optimize preprocessing and neural topology, achieving up to ~11x LUT reductions and substantial latency improvements while maintaining state-of-the-art fidelity. Through automated RTL generation and FPGA synthesis, LUNA demonstrates robust performance on standard superconducting readout data, supporting scalable quantum processors and QEC loops. The work highlights a practical path to compact, fast, and reliable qubit readout accelerators that can coexist with large-scale quantum control infrastructures.

Abstract

Qubit readout is a critical operation in quantum computing systems, which maps the analog response of qubits into discrete classical states. Deep neural networks (DNNs) have recently emerged as a promising solution to improve readout accuracy . Prior hardware implementations of DNN-based readout are resource-intensive and suffer from high inference latency, limiting their practical use in low-latency decoding and quantum error correction (QEC) loops. This paper proposes LUNA, a fast and efficient superconducting qubit readout accelerator that combines low-cost integrator-based preprocessing with Look-Up Table (LUT) based neural networks for classification. The architecture uses simple integrators for dimensionality reduction with minimal hardware overhead, and employs LogicNets (DNNs synthesized into LUT logic) to drastically reduce resource usage while enabling ultra-low-latency inference. We integrate this with a differential evolution based exploration and optimization framework to identify high-quality design points. Our results show up to a 10.95x reduction in area and 30% lower latency with little to no loss in fidelity compared to the state-of-the-art. LUNA enables scalable, low-footprint, and high-speed qubit readout, supporting the development of larger and more reliable quantum computing systems.

Paper Structure

This paper contains 29 sections, 4 equations, 4 figures, 4 tables.

Table of Contents

  1. Introduction
  2. Background and Related Work
  3. Qubit readout for superconducting devices
  4. LUT-based networks
  5. DSE and NAS
  6. LUNA vs. prior work
  7. The LUNA Approach
  8. Overview and design flow
  9. Architecture
  10. Integrator Based Preprocessor
  11. LogicNet classifier
  12. Design space
  13. Search and Optimization
  14. Composite cost and metric estimation
  15. Latency estimation.
  16. ...and 14 more sections

Figures (4)

  • Figure 1: Simplified superconducting-qubit readout chain. RFSoC-FPGA is responsible for qubit drive and readout.
  • Figure 2: LUNA co-design flow: (1) enumerate, (2) prune, (3) DE-based NAS, (4) generate RTL (integrator + LUT-DNN), (5) implement design on target device and evaluate fidelity on test set.
  • Figure 3: A high level overview of the LUNA architecture. Values shown are demonstrative; taken from our fidelity-optimized solution shown in Table \ref{['tab:nasresults']}.
  • Figure 4: Best cost trajectory across generations for each target objective: (a) Fidelity-optimized, (b) Latency-optimized, and (c) Area-optimized. Each curve shows the best individual’s cost per generation.