The Native Spiking Microarchitecture: From Iontronic Primitives to Bit-Exact FP8 Arithmetic

TL;DR

This work introduces a Native Spiking Microarchitecture that treats iontronic IF dynamics as a complete computational substrate capable of deterministic, bit-exact FP8 arithmetic. By building a spiking logic substrate, a bit-exact FP8 representation, and two arithmetic engines (including a spatial, $O(\log N)$-depth adder) plus a tree-based accumulation scheme, it demonstrates 100% bit-exact FP8 fidelity and a 17× reduction in Linear-Layer latency for Transformer-like workloads. The approach shows robustness to extreme leakage ($\beta \approx 0.01$) and noise up to $\sigma=0.15$, suggesting practical viability on imperfect post-silicon iontronic devices. While the end-to-end foundation-model validation remains future work, the framework provides a rigorous pathway to deterministic computation on stochastic substrates, enabling scalable, energy-efficient inference on MOF-based hardware.

Abstract

The 2025 Nobel Prize in Chemistry for Metal-Organic Frameworks (MOFs) and recent breakthroughs by Huanting Wang's team at Monash University establish angstrom-scale channels as promising post-silicon substrates with native integrate-and-fire (IF) dynamics. However, utilizing these stochastic, analog materials for deterministic, bit-exact AI workloads (e.g., FP8) remains a paradox. Existing neuromorphic methods often settle for approximation, failing Transformer precision standards. To traverse the gap "from stochastic ions to deterministic floats," we propose a Native Spiking Microarchitecture. Treating noisy neurons as logic primitives, we introduce a Spatial Combinational Pipeline and a Sticky-Extra Correction mechanism. Validation across all 16,129 FP8 pairs confirms 100% bit-exact alignment with PyTorch. Crucially, our architecture reduces Linear layer latency to O(log N), yielding a 17x speedup. Physical simulations further demonstrate robustness against extreme membrane leakage (beta approx 0.01), effectively immunizing the system against the stochastic nature of the hardware.