A manufacturable surface code architecture for spin qubits with fast transversal logic

TL;DR

The SNAQ (Shuttling-capable Narrow Array of spin Qubits) surface code architecture is proposed, which relaxes the 1:1 readout-to-qubit assumption by leveraging spin shuttling to time-multiplex ancilla qubit initialization and readout and provides a compelling path toward high-performance fault-tolerant computation on near-term-manufacturable spin qubit arrays.

Abstract

Spin qubits in silicon quantum dot arrays are a promising quantum computation platform for long-term scalability due to their small qubit footprint and compatibility with advanced semiconductor manufacturing. However, spin qubit devices face a key architectural bottleneck: the large physical footprint of readout components relative to qubits prevents a dense layout where all qubits can be measured simultaneously, complicating the implementation of quantum error correction. This challenge is offset by the platform's unique rapid shuttling capability, which can be used to transport qubits to distant readout ports. In this work, we explore the design constraints and capabilities of spin qubits in silicon and propose the SNAQ (Shuttling-capable Narrow Array of spin Qubits) surface code architecture, which relaxes the 1:1 readout-to-qubit assumption by leveraging spin shuttling to time-multiplex ancilla qubit initialization and readout. Our analysis shows that, given sufficiently high (experimentally demonstrated) qubit coherence times, SNAQ delivers an orders-of-magnitude reduction in chip area per logical qubit. Additionally, by using a denser grid of physical qubits, SNAQ enables fast transversal logic for short-distance logical operations, achieving 4.0-22.3x improvement in local logical clock speed while still supporting global operations via lattice surgery. This translates to a 57-60% reduction in spacetime cost of 15-to-1 magic state distillation, a key fault-tolerant subroutine. Our work pinpoints critical hardware metrics and provides a compelling path toward high-performance fault-tolerant computation on near-term-manufacturable spin qubit arrays.

Figures (13)

• Figure 1: (a) Depiction of a possible implementation of a 7-dot-wide array of quantum dots, similar to devices fabricated by industrial and academic groups philips_universal_2022borsoi_shared_2024henry_2d_2025ha_two-dimensional_2025george_12-spin-qubit_2025. Electrons (black) are held in place at the plunger gates (light gray) and can interact with their neighbors or shuttle to adjacent plungers by manipulating the voltages on the barrier gates (orange). Single-electron transistors (green) allow for qubit readout on the two sides of the array. (b) SNAQ achieves similar performance to baselines while improving chip area efficiency and wiring efficiency. (c) SNAQ avoids the downside of a longer syndrome extraction cycle by enabling transversal CNOTs (tCNOTs), achieving significantly faster logical clock speeds compared to lattice-surgery-based approaches.
• Figure 2: Proposed SNAQ (Shuttling-capable Narrow Array of spin Qubits) architecture. (a) For ease of visualization, we translate from the specific chip components in Figure \ref{['fig:hero']} to the abstract components we will use in the rest of the paper. Depicted is a layout of a distance-5 surface code patch on a 7-dot-wide array. Initialization and readout components (green) are only available on the edges of the array. Data qubits (dark gray) are interleaved with channels of empty dots (light gray) used to shuttle surface code ancilla qubits from edge to edge in the direction of the black arrows. Surface code X and Z stabilizers (blue and pink) are shown behind the array, supported on the data qubits. (b) A logical 1 $\times$ N layout of surface codes in a narrow array. (c) Possible design of a fully scalable architecture consisting of loops of SNAQ channels, with large spaces in between to allow for integration of control wires and readout.
• Figure 3: (a) Schedule of shuttle and CNOT/CZ operations that implement the surface code X and Z checks in a distance-preserving order. Each ancilla qubit is responsible for interacting with four data qubits in a rectangle, and it must interact in a specific order to avoid hook errors dennis_topological_2002, as shown in the lower right. (b) Serialized measurement of a group of ancilla qubits for readout density $\rho=1$. Ancilla qubits in group $i$ are measured first, followed by qubits in group $i+1$.
• Figure 4: Example pipeline schedule showing initialization, data entanglement, and measurement for two successive rounds of ancilla qubits, split into three waves each. The measurement of the first round of ancillae can be done simultaneously with the initialization of the second round. Any blank space in the schedule indicates idling, during which dynamical decoupling techniques could be used to improve coherence.
• Figure 5: Two possible implementations of multiqubit operations in the SNAQ architecture. (a) Lattice surgery can connect distant logical qubits via a channel of "routing patches" (lighter shaded stabilizers), which requires a wider dot array to support a second column of surface codes. (b) Spin shuttling enables transversal CNOT operations for sufficiently close tiles. Between stabilizer measurement rounds, physical qubits can shuttle past intermediate tiles to reach the target tile, then perform the transversal operation and shuttle back.