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Digital-Analog-Digital Quantum Supremacy

Daniel Lidar

TL;DR

The results imply that quantum-supremacy tests are possible on today's quantum annealers, as well as other devices capable of hybrid digital-analog quantum evolution, as well as other devices capable of hybrid digital-analog quantum evolution.

Abstract

Quantum supremacy has been explored extensively in gate-model settings. Here, we introduce a quantum-supremacy framework for a hybrid digital-analog-digital quantum computing (DADQC) model. We consider a device that applies an initial layer of single-qubit gates, a single transverse-field Ising analog block, and a final single-qubit layer before $Z$-basis readout. The analog block approximates $Z$-diagonal Ising evolution, and we prove that the resulting output distribution is within constant total-variation (TV) distance of an Instantaneous Quantum Polynomial-time (IQP) circuit. Our bounds and constructions are established for fully connected as well as bounded-degree hardware graphs, matching a variety of architectures, including trapped-ion, neutral atom, and superconducting platforms. Assuming anticoncentration (which we prove for all-to-all hardware graphs and conjecture for bounded-degree hardware graphs) and an average-case hardness conjecture for the associated complex-temperature Ising partition functions, standard reductions imply that any efficient classical sampler achieving constant TV error collapses the polynomial hierarchy. Our results imply that quantum-supremacy tests are possible on today's quantum annealers, as well as other devices capable of hybrid digital-analog quantum evolution.

Digital-Analog-Digital Quantum Supremacy

TL;DR

The results imply that quantum-supremacy tests are possible on today's quantum annealers, as well as other devices capable of hybrid digital-analog quantum evolution, as well as other devices capable of hybrid digital-analog quantum evolution.

Abstract

Quantum supremacy has been explored extensively in gate-model settings. Here, we introduce a quantum-supremacy framework for a hybrid digital-analog-digital quantum computing (DADQC) model. We consider a device that applies an initial layer of single-qubit gates, a single transverse-field Ising analog block, and a final single-qubit layer before -basis readout. The analog block approximates -diagonal Ising evolution, and we prove that the resulting output distribution is within constant total-variation (TV) distance of an Instantaneous Quantum Polynomial-time (IQP) circuit. Our bounds and constructions are established for fully connected as well as bounded-degree hardware graphs, matching a variety of architectures, including trapped-ion, neutral atom, and superconducting platforms. Assuming anticoncentration (which we prove for all-to-all hardware graphs and conjecture for bounded-degree hardware graphs) and an average-case hardness conjecture for the associated complex-temperature Ising partition functions, standard reductions imply that any efficient classical sampler achieving constant TV error collapses the polynomial hierarchy. Our results imply that quantum-supremacy tests are possible on today's quantum annealers, as well as other devices capable of hybrid digital-analog quantum evolution.

Paper Structure

This paper contains 6 theorems, 75 equations.

Key Result

Lemma 1

Let $U_{\mathrm{L}}=S^\dagger W^{\otimes n}$, $H_Z=\beta H_{\mathrm{I}}$, and let $U'_{\mathrm{R}}$ be an arbitrary unitary (not necessarily a product). Define Then the induced output distributions satisfy

Theorems & Definitions (11)

  • Lemma 1
  • Theorem 1: Supremacy for DADQC
  • Definition 1: QPU-restricted graph ensemble
  • Conjecture 1: QPU-restricted average-case Ising hardness
  • Conjecture 2: Anticoncentration for QPU-restricted IQP ensemble
  • Proposition 1: Anticoncentration for complete hardware graphs
  • Theorem 2: Supremacy for DADQC on a fixed $D$-regular hardware graph family
  • Lemma 2
  • proof
  • Lemma 3
  • ...and 1 more