Using Open Source EDA Tools in ASICs for HEP: A Mixed Comparison

TL;DR

This study benchmarks open-source EDA tools against a commercial flow in the IHP SG13G2 open PDK across three blocks: a CMN filter, an FSM, and a VCO, under identical constraints and PVT assumptions. The digital results show that open-source design can achieve functional 50 MHz implementations, but commercial flows generally yield smaller area and lower power, with more automated optimization; the analog VCO demonstrates feasibility with open tools but requires manual tuning to manage parasitics. The work provides a side-by-side quantification of quality of results for both digital and analog blocks, highlighting open-source viability for early prototyping and collaboration, while confirming commercial tools’ advantages for tight power/area targets and precision analog layout. This has practical implications for education, collaborative development, and rapid prototyping in HEP ASIC design, and sets the stage for broader evaluations across more blocks and silicon validation. $50$ MHz operation and a maximum $f_{osc}$ of $2.65$ GHz are key benchmarks demonstrated in the open PDK environment.

Abstract

This work compares open-source electronic design automation tools with a commercial environment using three representative integrated circuit blocks in the IHP 130 nm open PDK: a common-mode noise filter, a finite-state machine, and a voltage-controlled oscillator. The study reports design effort and quality of results for digital logic, including area, power, and timing closure, and examines analog layout feasibility. For the finite-state machine at 50 MHz, the open-source flow reached 0.029 mm$^2$ (post-layout) and 4.37 mW (estimated) with 828 standard cells, whereas the commercial flow achieved 0.019 mm$^2$ and 2.00 mW with 497 cells, corresponding to increases of 53\% in area and 118\% in power. The common-mode noise filter totals 1.879 mm$^2$ with 1703 flip-flops at 50 MHz. The voltage-controlled oscillator occupies 0.0025 mm$^2$ and achieves a simulated maximum oscillation frequency of 2.65 GHz. The contribution is a side-by-side quantification of quality of results across digital and analog blocks in the IHP open PDK. The results indicate that open-source tools are viable for early prototyping, training, and collaboration, while commercial flows retain advantages in automation and quality of results when strict targets on power and area or precision analog layout are required.

Figures (3)

• Figure 1: Schematics of the blocks implemented for comparison.
• Figure 2: Digital layouts under identical constraints. Layer colors are tool specific.
• Figure 3: VCO layout with magnified view of the ring core and device tiling. Layer colors are tool specific.