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When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generation

Yiwen Liang, Qiufeng Li, Shikai Wang, Weidong Cao

TL;DR

This work tackles reliability challenges in LLM-driven hardware code generation arising from memorization of proprietary or unsafe patterns. It introduces a domain-specific unlearning framework that combines syntax-preserving unlearning with FiFSL, a margin-based, floor-aware selective loss, to forget problematic knowledge while preserving RTL syntax and functional integrity. The approach enables up to 3x larger forget sets and typically requires only one training epoch, while maintaining performance on held-out RTL benchmarks and generalization to unseen tasks. Empirical results across multiple RTL-tuned LLMs and benchmarks demonstrate improved forgetting-utility trade-offs, strong efficiency, and broad applicability to reliable hardware design.

Abstract

Large Language Models (LLMs) have shown strong potential in accelerating digital hardware design through automated code generation. Yet, ensuring their reliability remains a critical challenge, as existing LLMs trained on massive heterogeneous datasets often exhibit problematic memorization of proprietary intellectual property (IP), contaminated benchmarks, and unsafe coding patterns. To mitigate these risks, we propose a novel unlearning framework tailored for LLM-based hardware code generation. Our method combines (i) a syntax-preserving unlearning strategy that safeguards the structural integrity of hardware code during forgetting, and (ii) a fine-grained floor-aware selective loss that enables precise and efficient removal of problematic knowledge. This integration achieves effective unlearning without degrading LLM code generation capabilities. Extensive experiments show that our framework supports forget sets up to 3x larger, typically requiring only a single training epoch, while preserving both syntactic correctness and functional integrity of register-transfer level (RTL) codes. Our work paves an avenue towards reliable LLM-assisted hardware design.

When Forgetting Builds Reliability: LLM Unlearning for Reliable Hardware Code Generation

TL;DR

This work tackles reliability challenges in LLM-driven hardware code generation arising from memorization of proprietary or unsafe patterns. It introduces a domain-specific unlearning framework that combines syntax-preserving unlearning with FiFSL, a margin-based, floor-aware selective loss, to forget problematic knowledge while preserving RTL syntax and functional integrity. The approach enables up to 3x larger forget sets and typically requires only one training epoch, while maintaining performance on held-out RTL benchmarks and generalization to unseen tasks. Empirical results across multiple RTL-tuned LLMs and benchmarks demonstrate improved forgetting-utility trade-offs, strong efficiency, and broad applicability to reliable hardware design.

Abstract

Large Language Models (LLMs) have shown strong potential in accelerating digital hardware design through automated code generation. Yet, ensuring their reliability remains a critical challenge, as existing LLMs trained on massive heterogeneous datasets often exhibit problematic memorization of proprietary intellectual property (IP), contaminated benchmarks, and unsafe coding patterns. To mitigate these risks, we propose a novel unlearning framework tailored for LLM-based hardware code generation. Our method combines (i) a syntax-preserving unlearning strategy that safeguards the structural integrity of hardware code during forgetting, and (ii) a fine-grained floor-aware selective loss that enables precise and efficient removal of problematic knowledge. This integration achieves effective unlearning without degrading LLM code generation capabilities. Extensive experiments show that our framework supports forget sets up to 3x larger, typically requiring only a single training epoch, while preserving both syntactic correctness and functional integrity of register-transfer level (RTL) codes. Our work paves an avenue towards reliable LLM-assisted hardware design.

Paper Structure

This paper contains 22 sections, 10 equations, 3 figures, 4 tables, 1 algorithm.

Table of Contents

  1. Introduction
  2. Background
  3. Syntax and Semantics of Hardware Description Language
  4. Hardware Design with LLM
  5. Machine Unlearning
  6. Methodology
  7. Framework Overview
  8. Problem Definition
  9. Proposed Unlearning Framework
  10. Syntax-Preserving Unlearning
  11. FiFSL: Fine-grained Floor-aware Selective Loss
  12. Summary of the Proposed Strategy
  13. Experiments
  14. Experimental Methodology
  15. Evaluation Metrics
  16. ...and 7 more sections

Figures (3)

  • Figure 1: Overview of our proposed domain-specific LLM unlearning framework for reliable hardware code generation (HW-gen).
  • Figure 2: Syntax-preserving unlearning: source Verilog (a) vs. syntax-preserving Verilog (b). The preserved syntax is masked in gray.
  • Figure 3: Comparisons of forgetting quality and model utility across unlearning methods, varying forget-set sizes, and different LLMs. Ideal unlearning target: $(1.0, 1.0)$, perfect forgetting with no utility loss. Our method achieves comparable or better trade-offs in only 1 epoch, while baselines require 4$\sim$7 epochs.