Maestro: Intelligent Execution for Quantum Circuit Simulation
Oriol Bertomeu, Hamzah Ghayas, Adrian Roman, Stephen DiAdamo
TL;DR
The paper tackles the fragmentation of quantum circuit simulators by introducing Maestro, a unified, extensible interface that orchestrates multiple backends via a common intermediate representation and a predictive runtime model. It integrates state-vector, MPS, tensor-network, stabilizer, GPU-accelerated, and p-block methods, with GPU paths and distributed computing support, optimized for HPC environments. A data-driven backend-prediction engine selects the fastest simulator for each circuit, enabling efficient batched and distributed workloads. Benchmark results show significant throughput gains across single and multi-circuit scenarios, validating Maestro’s utility for hybrid quantum-classical workflows and large-scale HPC deployments.
Abstract
Quantum circuit simulation remains essential for developing and validating quantum algorithms, especially as current quantum hardware is limited in scale and quality. However, the growing diversity of simulation methods and software tools creates a high barrier to selecting the most suitable backend for a given circuit. We introduce Maestro, a unified interface for quantum circuit simulation that integrates multiple simulation paradigms - state vector, MPS, tensor network, stabilizer, GPU-accelerated, and p-block methods - under a single API. Maestro includes a predictive runtime model that automatically selects the optimal simulator based on circuit structure and available hardware, and applies backend-specific optimizations such as multiprocessing, GPU execution, and improved sampling. Benchmarks across heterogeneous workloads demonstrate that Maestro outperforms individual simulators in both single-circuit and large batched settings, particularly in high-performance computing environments. Maestro provides a scalable, extensible platform for quantum algorithm research, hybrid quantum-classical workflows, and emerging distributed quantum computing architectures.
